Transmitting apparatus and signal processing method thereof

ABSTRACT

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns including a plurality of rows, respectively, and comprises: a block interleaver configured to divide each of the plurality of columns into a first part and a second part, and interleave a plurality of bit groups constituting the LDPC codeword, all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part, at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns constituting the second part.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit under 35 U.S.C. §119 from U.S. Provisional Application No. 61/882,774 field on Sep. 26, 2013 in the United States Patent and Trademark Office and Korean Patent Application No. 10-2014-0129604 filed on Sep. 26, 2014 in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety.

BACKGROUND

1. Technical Field

Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and a signal processing method thereof, and more particularly, to a transmitting apparatus which processes data and transmits the data, and a signal processing method thereof.

2. Description of the Related Art

In a communication/broadcasting system, link performance may greatly deteriorate due to various noises of channels, a fading phenomenon, and an inter-symbol interference (ISI). Therefore, in order to implement high digital communication/broadcasting systems requiring high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and portable Internet, there is a demand for a method for overcoming the noise, fading, and inter-symbol interference. To overcome the noise, etc., research on an error-correction code has been actively conducted in recent years as a method for effectively restoring distorted information and enhancing reliability of communication.

The Low Density Parity Check (LDPC) code which was first introduced by Gallager in the 1960s has been forgotten for a long time due to its difficulty and complexity in realizing by the level of technology at that time. However, as the turbo code which was suggested by Berrou, Glavieux, Thitimajshima in 1993 showed performance equivalent to the channel capacity of Shannon, the performance and characteristics of the turbo code were actively interpreted and many researches on channel encoding based on iterative decoding and graph were conducted. This leaded the re-research on the LDPC code in the late 1990's and it turned out that decoding by applying iterative decoding based on a sum-product algorithm on a Tanner graph corresponding to the LDPC code resulted in the performance equivalent to the channel capacity of Shannon.

When the LDPC code is transmitted by using a high order modulation scheme, performance depends on how codeword bits are mapped onto high order modulation bits. Therefore, there is a need for a method for mapping LDPC codeword bits onto high order modulation bits to obtain an LDPC code of good performance.

SUMMARY

One or more exemplary embodiments may overcome the above disadvantages and other disadvantages not described above. However, it is understood that one or more exemplary embodiment are not required to overcome the disadvantages described above, and may not overcome any of the problems described above.

One or more exemplary embodiments provide a transmitting apparatus which can map a bit included in a predetermined group from among a plurality of groups of a Low Density Parity Check (LDPC) codeword onto a predetermined bit of a modulation symbol, and transmit the bit, and a signal processing method thereof.

According to an aspect of an exemplary embodiment, there is provided a transmitting apparatus including: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol, and the interleaver is formed of a plurality of columns including a plurality of rows, respectively, and include a block interleaver configured to divide each of the plurality of columns into a first part and a second part, and interleave a plurality of bit groups constituting the LDPC codeword, and all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part, and wherein at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns constituting the second part.

The number of the plurality of columns may be a same as a modulation degree according to the modulation method, and each of the plurality of columns may be formed of rows of which number is the number of bits constituting an LDPC codeword divided by the number of the plurality of columns.

The first part may be formed of rows of which number is the number of bits included in at least a part of bit groups which are writable in each of the plurality of columns by a bit group unit from among a plurality of bit groups constituting the LDPC codeword according to the number of columns constituting the block interleaver, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group, from each of the plurality of columns, and the second part may be formed of rows excluding the number of rows as many as the number of bits included in at least a part of bit groups which are writable in each of the plurality of columns in bit group units from rows constituting each of the plurality of columns, from each of the plurality of columns.

The number of rows of the second part may be a same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver.

The block interleaver may write the bits included in at least a part of bit groups which are writable in bit group units in each of a plurality of columns constituting the first part sequentially, divide bits included in remaining bit groups excluding at least a part of bit groups from a plurality of bit groups based on the number of the plurality of columns, and write the bits in each of a plurality of columns constituting the second part sequentially.

The block interleaver may divide bits included in the remaining bit groups by the number of the plurality of columns, write each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and perform interleaving by reading a plurality of columns constituting the second part in a row direction.

The modulation degree may be 2, 4, 6, 8, 10, or 12 when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM, respectively.

According to an aspect of an exemplary embodiment, there is provided a method for processing a signal of a transmitting apparatus including: generating an LDPC codeword by performing LDPC encoding; interleaving the LDPC codeword; and generating a modulation symbol by modulating the interleaved LDPC codeword according to a modulation method, and the interleaving interleaves a plurality of bit groups constituting the LDPC codeword by dividing each of a plurality of columns including each of a plurality of rows into a first part and a second part, all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part, and at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns constituting the second part.

The number of the plurality of columns may be a same as a modulation degree according to the modulation method, and each of the plurality of columns may be formed of rows of which number is the number of bits constituting an LDPC codeword divided by the number of the plurality of columns.

The first part may be formed of rows of which number is the number of bits included in at least a part of bit groups which are writable in each of the plurality of columns by a bit group unit from among a plurality of bit groups constituting the LDPC codeword according to the number of columns constituting the block interleaver, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group, from each of the plurality of columns, and the second part may be formed of rows excluding the number of rows as many as the number of bits included in at least a part of bit groups which are writable in each of the plurality of columns in bit group units from rows constituting each of the plurality of columns, from each of the plurality of columns.

The number of rows of the second part may be a same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver.

The interleaving may include writing the bits included in at least a part of bit groups which are writable in bit group units in each of a plurality of columns constituting the first part sequentially, dividing bits included in remaining bit groups excluding at least a part of bit groups from a plurality of bit groups based on the number of the plurality of columns, and writing the bits in each of a plurality of columns constituting the second part sequentially.

The interleaving may include dividing bits included in the remaining bit groups by the number of the plurality of columns, writing each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and performing interleaving by reading a plurality of columns constituting the second part in a row direction.

The modulation degree may be 2, 4, 6, 8, 10, or 12 when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or other aspects will be more apparent by describing in detail exemplary embodiments, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram to illustrate a configuration of a transmitting apparatus according to an exemplary embodiment;

FIGS. 2 and 3 are views to illustrate a configuration of a parity check matrix according to exemplary embodiments;

FIG. 4 is a block diagram to illustrate a configuration of an interleaver according to an exemplary embodiment;

FIGS. 5 to 7 are views illustrating a method for processing an LDPC codeword on a group basis according to exemplary embodiments;

FIGS. 8 to 11 are views to illustrate a configuration of a block interleaver and an interleaving method according to exemplary embodiments;

FIGS. 12 and 13 are views to illustrate an operation of a demultiplexer according to exemplary embodiments;

FIG. 14 is a view to illustrate an example of a uniform constellation modulation method according to an exemplary embodiment;

FIGS. 15 to 19 are views to illustrate an example of a non-uniform constellation modulation method according to exemplary embodiments;

FIG. 20 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment;

FIG. 21 is a block diagram to illustrate a configuration of a deinterleaver according to exemplary embodiments;

FIG. 22 is a view to illustrate a block deinterleaver according to an exemplary embodiment; and

FIG. 23 is a flowchart to illustrate a signal processing method according to an exemplary embodiment.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Hereinafter, various exemplary embodiments will be described in greater detail with reference to the accompanying drawings.

In the following description, same reference numerals are used for the same elements when they are depicted in different drawings. The matters defined in the description, such as detailed construction and elements, are provided to assist in a comprehensive understanding of the exemplary embodiments. Thus, it is apparent that the exemplary embodiments can be carried out without those specifically defined matters. Also, functions or elements known in the related art are not described in detail since they would obscure the exemplary embodiments with unnecessary detail.

FIG. 1 is a block diagram to illustrate a configuration of a transmitting apparatus according to a first exemplary embodiment. Referring to FIG. 1, the transmitting apparatus 100 includes an encoder 110, an interleaver 120, and a modulator 130 (or a constellation mapper).

The encoder 110 generates a Low Density Parity Check (LDPC) codeword by performing LDPC encoding. The encoder 110 may include an LDPC encoder (not shown) to perform the LDPC encoding.

Specifically, the encoder 110 LDPC-encodes input bits to information word bits to generate the LDPC codeword which is formed of the information word bits and parity bits (that is, LDPC parity bits). Here, since an LDPC code for the LDPC encoding is a systematic code, the information word bits may be included in the LDPC codeword as they are.

The LDPC codeword is formed of the information word bits and the parity bits. For example, the LDPC codeword is formed of N_(ldpc) number of bits, and includes K_(ldpc) number of information word bits and N_(parity)=N_(ldpc)−K_(ldpc) number of parity bits.

In this case, the encoder 110 may generate the LDPC codeword by performing the LDPC encoding based on a parity check matrix. That is, since the LDPC encoding is a process for generating an LDPC codeword to satisfy H·C^(T)=0, the encoder 110 may use the parity check matrix when performing the LDPC encoding. Herein, H is a parity check matrix and C is an LDPC codeword.

For the LDPC encoding, the transmitting apparatus 100 may include a separate memory and may pre-store parity check matrices of various formats.

For example, the transmitting apparatus 100 may pre-store parity check matrices which are defined in Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video Broadcasting-Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second Generation Terrestrial (DVB-T2), etc., or may pre-store parity check matrices which are defined in the North America digital broadcasting standard system Advanced Television System Committee (ATSC) 3.0 standards, which are currently being established. However, this is merely an example and the transmitting apparatus 100 may pre-store parity check matrices of other formats in addition to these parity check matrices.

Hereinafter, a configuration of a parity check matrix will be explained in detail with reference to FIGS. 2 and 3.

First, referring to FIG. 2, a parity check matrix 200 is formed of an information word submatrix 210 corresponding to information word bits, and a parity submatrix 220 corresponding to parity bits. In the parity check matrix 200, elements other than elements with 1 have 0.

The information word submatrix 210 includes K_(ldpc) number of columns and the parity submatrix 220 includes N_(parity)=N_(ldpc)−K_(ldpc) number of columns. The number of rows of the parity check matrix 200 is identical to the number of columns of the parity submatrix 220, N_(parity)=N_(ldpc)−K_(ldpc).

In addition, in the parity check matrix 200, N_(ldpc) is a length of an LDPC codeword, K_(ldpc) is a length of information word bits, and N_(parity)=N_(ldpc)−K_(ldpc) is a length of parity bits. The length of the LDPC codeword, the information word bits, and the parity bits mean the number of bits included in each of the LDPC codeword, the information bits, and the parity bits.

Hereinafter, the configuration of the information word submatrix 210 and the parity submatrix 220 will be explained in detail.

The information word submatrix 210 includes K_(ldpc) number of columns (that is, 0^(th) column to (K_(ldpc)−1)^(th) column), and follows the following rules:

First, M number of columns from among K_(ldpc) number of columns of the information word submatrix 210 belong to the same group, and K_(ldpc) number of columns is divided into K_(ldpc)/M number of column groups. In each column group, a column is cyclic-shifted from an immediately previous column by Q_(ldpc) or Q_(ldpc) number of bits.

Herein, M is an interval at which a pattern of a column group, which includes a plurality of columns, is repeated in the information word submatrix 210 (e.g., M=360), and Q_(ldpc) is a size by which one column is cyclic-shifted from an immediately previous column in a same column group in the information word submatrix 210. M and Q_(ldpc) are integers and are determined to satisfy Q_(ldpc)=(N_(ldpc)−K_(ldpc))/M. In this case, K_(ldpc)/M is also an integer. M and Q_(ldpc) may have various values according to a length of the LDPC codeword and a code rate.

For example, when M=360 and the length of the LDPC codeword, N_(ldpc), is 64800, Q_(ldpc) may be defined as in table 1 presented below, and, when M=360 and the length N_(ldpc) of the LDPC codeword is 16200, Q_(ldpc) may be defined as in table 2 presented below.

TABLE 1 Code Rate N_(ldpc) M Q_(ldpc) 5/15  64800 360 120 6/15 64800 360 108 7/15 64800 360 96 8/15 64800 360 84 9/15 64800 360 72 10/15  64800 360 60 11/15  64800 360 48 12/15  64800 360 36 13/15  64800 360 24

TABLE 2 Code Rate N_(ldpc) M Q_(ldpc) 5/15 16200 360 30 6/15 16200 360 27 7/15 16200 360 24 8/15 16200 360 21 9/15 16200 360 18 10/15  16200 360 15 11/15  16200 360 12 12/15  16200 360 9 13/15  16200 360 6

Second, when the degree of the 0^(th) column of the i^(th) column group (i=0, 1, . . . , K_(ldpc)/M−1) is Di (herein, the degree is the number of value 1 existing in each column and all columns belonging to the same column group have the same degree), and a position (or an index) of each row where 1 exists in the 0^(th) column of the i^(th) column group is R_(i,0) ⁽⁰⁾, R_(i,0) ⁽¹⁾, . . . , R_(i,0) ^((D) ^(i) ⁻¹⁾, an index R_(i,j) ^((k)) of a row where k weight-1 is located in the j^(th) column in the i^(th) column group (that is, an index of a row where k^(th) is located in the j^(th) column in the i^(th) column group) is determined by following Equation 1:

R _(i,j) ^((k)) =R _(i,(j−1)) ^((k)) +Q _(ldpc) mod(N _(ldpc) −K _(ldpc))  (1)

where k=0, 1, 2, . . . D_(i)−1; i=0, 1, . . . , K_(ldpc)/M−1; and j=1, 2, . . . , M−1.

Equation 1 can be expressed as following Equation 2:

R _(i,j) ^((k)) ={R _(i,0) ^((k))+(j mod M)×Q _(ldpc)} mod(N _(ldpc) −K _(ldpc))  (2)

where k=0, 1, 2, . . . D_(i)−1; i=0, 1, . . . , K_(ldpc)/M−1; and j=1, 2, . . . , M−1.

In the above equations, R_(i,j) ^((k)) is an index of a row where k^(th) weight-1 is located in the j^(th) column in the i^(th) column group, N_(ldpc) is a length of an LDPC codeword, K_(ldpc) is a length of information word bits, D_(i) is a degree of columns belonging to the i^(th) column group, M is the number of columns belonging to a single column group, and Q_(ldpc) is a size by which each column in the column group is cyclic-shifted.

As a result, referring to these equations, when only R_(i,0) ^((k)) is known, the index R_(i,j) ^((k)) of the row where the k^(th) weight-1 is located in the j^(th) column in the i^(th) column group can be known. Therefore, when the index value of the row where the k^(th) weight-1 is located in the first column of each column group is stored, a position of column and row where weight-1 is located in the parity check matrix 200 having the configuration of FIG. 2 (that is, in the information word submatrix 210 of the parity check matrix 200) can be known.

According to the above-described rules, all of the columns belonging to the i^(th) column group have the same degree D_(i). Accordingly, the LDPC codeword which stores information on the parity check matrix according to the above-described rules may be briefly expressed as follows.

For example, when N_(ldpc) is 30, K_(ldpc) is 15, and Q_(ldpc) is 3, position information of the row where weight-1 is located in the 0^(th) column of the three column groups may be expressed by a sequence of Equations 3 and may be referred to as “weight-1 position sequence”.

R _(1,0) ⁽¹⁾=1, R _(1,0) ⁽²⁾=2, R _(1,0) ⁽³⁾=8, R _(1,0) ⁽⁴⁾=10,

R _(2,0) ⁽¹⁾=0, R _(2,0) ⁽²⁾=9, R _(2,0) ⁽³⁾=13,

R _(3,0) ⁽¹⁾=0, R _(3,0) ⁽²⁾=14.  (3),

where R_(i,j) ^((k)) is an index of a row where k^(th) weight-1 is located in the j^(th) column in the i^(th) column group.

The weight-1 position sequence like Equation 3 which expresses an index of a row where 1 is located in the 0^(th) column of each column group may be briefly expressed as in Table 3 presented below:

TABLE 3 1 2 8 10 0 9 13 0 14

Table 3 shows positions of elements having weight-1, that is, the value 1, in the parity check matrix, and the i^(th) weight-1 position sequence is expressed by indexes of rows where weight-1 is located in the 0^(th) column belonging to the i^(th) column group.

The information word submatrix 210 of the parity check matrix according to an exemplary embodiment may be defined as in Tables 4 to 11 presented below, based on the above descriptions.

Specifically, Tables 4 to 11 show indexes of rows where 1 is located in the 0^(th) column of the i^(th) column group of the information word submatrix 210. That is, the information word submatrix 210 is formed of a plurality of column groups each including M number of columns, and positions of 1 in the 0^(th) column of each of the plurality of column groups may be defined by Tables 4 to 11.

Herein, the indexes of the rows where 1 is located in the 0^(th) column of the i^(th) column group mean “addresses of parity bit accumulators”. The “addresses of parity bit accumulators” have the same meaning as defined in the DVB-C2/S2/T2 standards or the ATSC 3.0 standards which are currently being established, and thus, a detailed explanation thereof is omitted.

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate R is 6/15, and M is 360, the indexes of the rows where 1 is located in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are as shown in Table 4 presented below:

TABLE 4 i Index of row where 1 is located in the 0th column of the ith column group 0 1606 3402 4961 6751 7132 11516 12300 12482 12592 13342 13764 14123 21576 23946 24533 25376 25667 26836 31799 34173 35462 36153 36740 37085 37152 37468 37658 1 4621 5007 6910 8732 9757 11508 13099 15513 16335 18052 19512 21319 23663 25628 27208 31333 32219 33003 33239 33447 36200 36473 36938 37201 37283 37495 38642 2 16 1094 2020 3080 4194 5098 5631 6877 7889 8237 9804 10067 11017 11366 13136 13354 15379 18934 20199 24522 26172 28666 30386 32714 36390 37015 37162 3 700 897 1708 6017 6490 7372 7825 9546 10398 16605 18561 18745 21625 22137 23693 24340 24966 25015 26995 28586 28895 29687 33938 34520 34858 37056 38297 4 159 2010 2573 3617 4452 4958 5556 5832 6481 8227 9924 10836 14954 15594 16623 18065 19249 22394 22677 23408 23731 24076 24776 27007 28222 30343 38371 5 3118 3545 4768 4992 5227 6732 8170 9397 10522 11508 15536 20218 21921 28599 29445 29758 29968 31014 32027 33685 34378 35867 36323 36728 36870 38335 38623 6 1264 4254 6936 9165 9486 9950 10861 11653 13697 13961 15164 15665 18444 19470 20313 21189 24371 26431 26999 28086 28251 29261 31981 34015 35850 36129 37186 7 111 1307 1628 2041 2524 5358 7988 8191 10322 11905 12919 14127 15515 15711 17061 19024 21195 22902 23727 24401 24608 25111 25228 27338 35398 37794 38196 8 961 3035 7174 7948 13355 13607 14971 18189 18339 18665 18875 19142 20615 21136 21309 21758 23366 24745 25849 25962 27583 30006 31118 32106 36469 36583 37920 9 2990 3549 4273 4808 5707 6021 6509 7456 8240 10044 12262 12660 13085 14750 15680 16049 21587 23997 25803 28343 28693 34393 34860 35490 36021 37737 38296 10 955 4323 5145 6885 8123 9730 11840 12216 19194 20313 23056 24248 24830 25268 26617 26801 28557 29753 30745 31450 31973 32839 33025 33296 35710 37366 37509 11 264 605 4181 4483 5156 7238 8863 10939 11251 12964 16254 17511 20017 22395 22818 23261 23422 24064 26329 27723 28186 30434 31956 33971 34372 36764 38123 12 520 2562 2794 3528 3860 4402 5676 6963 8655 9018 9783 11933 16336 17193 17320 19035 20606 23579 23769 24123 24966 27866 32457 34011 34499 36620 37526 13 10106 10637 10906 34242 14 1856 15100 19378 21848 15 943 11191 27806 29411 16 4575 6359 13629 19383 17 4476 4953 18782 24313 18 5441 6381 21840 35943 19 9638 9763 12546 30120 20 9587 10626 11047 25700 21 4088 15298 28768 35047 22 2332 6363 8782 28863 23 4625 4933 28298 30289 24 3541 4918 18257 31746 25 1221 25233 26757 34892 26 8150 16677 27934 30021 27 8500 25016 33043 38070 28 7374 10207 16189 35811 29 611 18480 20064 38261 30 25416 27352 36089 38469 31 1667 17614 25839 32776 32 4118 12481 21912 37945 33 5573 13222 23619 31271 34 18271 26251 27182 30587 35 14690 26430 26799 34355 36 13688 16040 20716 34558 37 2740 14957 23436 32540 38 3491 14365 14681 36858 39 4796 6238 25203 27854 40 1731 12816 17344 26025 41 19182 21662 23742 27872 42 6502 13641 17509 34713 43 12246 12372 16746 27452 44 1589 21528 30621 34003 45 12328 20515 30651 31432 46 3415 22656 23427 36395 47 632 5209 25958 31085 48 619 3690 19648 37778 49 9528 13581 26965 36447 50 2147 26249 26968 28776 51 15698 18209 30683 52 1132 19888 34111 53 4608 25513 38874 54 475 1729 34100 55 7348 32277 38587 56 182 16473 33082 57 3865 9678 21265 58 4447 20151 27618 59 6335 14371 38711 60 704 9695 28858 61 4856 9757 30546 62 1993 19361 30732 63 756 28000 29138 64 3821 24076 31813 65 4611 12326 32291 66 7628 21515 34995 67 1246 13294 30068 68 6466 33233 35865 69 14484 23274 38150 70 21269 36411 37450 71 23129 26195 37653

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate R is 7/15, and M is 360, the indexes of the rows where 1 is located in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are as shown in Table 5 presented below:

TABLE 5 i Index of row where 1 is located in the 0th column of the ith column group 0 7 15 26 69 1439 3712 5756 5792 5911 8456 10579 19462 19782 21709 23214 25142 26040 30206 30475 31211 31427 32105 32989 33082 33502 34116 34241 34288 34292 34318 34373 34390 34465 1 83 1159 2271 6500 6807 7823 10344 10700 13367 14162 14242 14352 15015 17301 18952 20811 24974 25795 27868 28081 33077 33204 33262 33350 33516 33677 33680 33930 34090 34250 34290 34377 34398 2 25 2281 2995 3321 6006 7482 8428 11489 11601 14011 17409 26210 29945 30675 31101 31355 31421 31543 31697 32056 32216 33282 33453 33487 33696 34044 34107 34213 34247 34261 34276 34467 34495 3 0 43 87 2530 4485 4595 9951 11212 12270 12344 15566 21335 24699 26580 28518 28564 28812 29821 30418 31467 31871 32513 32597 33187 33402 33706 33838 33932 33977 34084 34283 34440 34473 4 81 3344 5540 7711 13308 15400 15885 18265 18632 22209 23657 27736 29158 29701 29845 30409 30654 30855 31420 31604 32519 32901 33267 33444 33525 33712 33878 34031 34172 34432 34496 34502 34541 5 42 50 66 2501 4706 6715 6970 8637 9999 14555 22776 26479 27442 27984 28534 29587 31309 31783 31907 31927 31934 32313 32369 32830 33364 33434 33553 33654 33725 33889 33962 34467 34482 6 6534 7122 8723 13137 13183 15818 18307 19324 20017 26389 29326 31464 32678 33668 34217 7 50 113 2119 5038 5581 6397 6550 10987 22308 25141 25943 29299 30186 33240 33399 8 7262 8787 9246 10032 10505 13090 14587 14790 16374 19946 21129 25726 31033 33660 33675 9 5004 5087 5291 7949 9477 11845 12698 14585 15239 17486 18100 18259 21409 21789 24280 10 28 82 3939 5007 6682 10312 12485 14384 21570 25512 26612 26854 30371 31114 32689 11 437 3055 9100 9517 12369 19030 19950 21328 24196 24236 25928 28458 30013 32181 33560 12 18 3590 4832 7053 8919 21149 24256 26543 27266 30747 31839 32671 33089 33571 34296 13 2678 4569 4667 6551 7639 10057 24276 24563 25818 26592 27879 28028 29444 29873 34017 14 72 77 2874 9092 10041 13669 20676 20778 25566 28470 28888 30338 31772 32143 33939 15 296 2196 7309 11901 14025 15733 16768 23587 25489 30936 31533 33749 34331 34431 34507 16 6 8144 12490 13275 14140 18706 20251 20644 21441 21938 23703 34190 34444 34463 34495 17 5108 14499 15734 19222 24695 25667 28359 28432 30411 30720 34161 34386 34465 34511 34522 18 61 893042 5524 12128 22505 22700 22919 24454 30526 33437 34114 34188 34490 34502 19 11 83 4668 4856 6361 11633 15342 16393 16958 26613 29136 30917 32559 34346 34504 20 3185 9728 25062 21 1643 5531 21573 22 2285 6088 24083 23 78 14678 19119 24 49 13705 33535 25 21192 32280 32781 26 10753 21469 22084 27 10082 11950 13889 28 7861 25107 29167 29 14051 34171 34430 30 706 894 8316 31 29693 30445 32281 32 10202 30964 34448 33 15815 32453 34463 34 4102 21608 24740 35 4472 29399 31435 36 1162 7118 23226 37 4791 33548 34096 38 1084 34099 34418 39 1765 20745 33714 40 1302 21300 33655 41 33 8736 16646 42 53 18671 19089 43 21 572 2028 44 3339 11506 16745 45 285 6111 12643 46 27 10336 11586 47 21046 32728 34538 48 22215 24195 34026 49 19975 26938 29374 50 16473 26777 34212 51 20 29260 32784 52 35 31645 32837 53 26132 34410 34495 54 12446 20649 26851 55 6796 10992 31061 56 0 46 8420 57 10 636 22885 58 7183 16342 18305 59 1 5604 28258 60 6071 18675 34489 61 16786 25023 33323 62 3573 5081 10925 63 5067 31761 34415 64 3735 33534 34522 65 85 32829 34518 66 6555 23368 34559 67 22083 29335 29390 68 6738 21110 34316 69 120 4192 11123 70 3313 4144 20824 71 27783 28550 31034 72 6597 8164 34427 73 18009 23474 32460 74 94 6342 12656 75 17 31962 34535 76 15091 24955 28545 77 15 3213 28298 78 26562 30236 34537 79 16832 20334 24628 80 4841 20669 26509 81 18055 23700 34534 82 23576 31496 34492 83 10699 13826 34440

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate R is 8/15, and M is 360, the indexes of the rows where 1 is located in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are as shown in Table 6 presented below:

TABLE 6 i Index of row where 1 is located in the 0th column of the ith column group 0 2768 3039 4059 5856 6245 7013 8157 9341 9802 10470 11521 12083 16610 18361 20321 24601 27420 28206 29788 1 2739 8244 8891 9157 12624 12973 15534 16622 16919 18402 18780 19854 20220 20543 22306 25540 27478 27678 28053 2 1727 2268 6246 7815 9010 9556 10134 10472 11389 14599 15719 16204 17342 17666 18850 22058 25579 25860 29207 3 28 1346 3721 5565 7019 9240 12355 13109 14800 16040 16839 17369 17631 19357 19473 19891 20381 23911 29683 4 869 2450 4386 5316 6160 7107 10362 11132 11271 13149 16397 16532 17113 19894 22043 22784 27383 28615 28804 5 508 4292 5831 8559 10044 10412 11283 14810 15888 17243 17538 19903 20528 22090 22652 27235 27384 28208 28485 6 389 2248 5840 6043 7000 9054 11075 11760 12217 12565 13587 15403 19422 19528 21493 25142 27777 28566 28702 7 1015 2002 5764 6777 9346 9629 11039 11153 12690 13068 13990 16841 17702 20021 24106 26300 29332 30081 30196 8 1480 3084 3467 4401 4798 5187 7851 11368 12323 14325 14546 16360 17158 18010 21333 25612 26556 26906 27005 9 6925 8876 12392 14529 15253 15437 19226 19950 20321 23021 23651 24393 24653 26668 27205 28269 28529 29041 29292 10 2547 3404 3538 4666 5126 5468 7695 8799 14732 15072 15881 17410 18971 19609 19717 22150 24941 27908 29018 11 888 1581 2311 5511 7218 9107 10454 12252 13662 15714 15894 17025 18671 24304 25316 25556 28489 28977 29212 12 1047 1494 1718 4645 5030 6811 7868 8146 10611 15767 17682 18391 22614 23021 23763 25478 26491 29088 29757 13 59 1781 1900 3814 4121 8044 8906 9175 11156 14841 15789 16033 16755 17292 18550 19310 22505 29567 29850 14 1952 3057 4399 9476 10171 10769 11335 11569 15002 19501 20621 22642 23452 24360 25109 25290 25828 28505 29122 15 2895 3070 3437 4764 4905 6670 9244 11845 13352 13573 13975 14600 15871 17996 19672 20079 20579 25327 27958 16 612 1528 2004 4244 4599 4926 5843 7684 10122 10443 12267 14368 18413 19058 22985 24257 26202 26596 27899 17 1361 2195 4146 6708 7158 7538 9138 9998 14862 15359 16076 18925 21401 21573 22503 24146 24247 27778 29312 18 5229 6235 7134 7655 9139 13527 15408 16058 16705 18320 19909 20901 22238 22437 23654 25131 27550 28247 29903 19 697 2035 4887 5275 6909 9166 11805 15338 16381 18403 20425 20688 21547 24590 25171 26726 28348 29224 29412 20 5379 17329 22659 23062 21 11814 14759 22329 22936 22 2423 2811 10296 12727 23 8460 15260 16769 17290 24 14191 14608 29536 30187 25 7103 10069 20111 22850 26 4285 15413 26448 29069 27 548 2137 9189 10928 28 4581 7077 23382 23949 29 3942 17248 19486 27922 30 8668 10230 16922 26678 31 6158 9980 13788 28198 32 12422 16076 24206 29887 33 8778 10649 18747 22111 34 21029 22677 27150 28980 35 7918 15423 27672 27803 36 5927 18086 23525 37 3397 15058 30224 38 24016 25880 26268 39 1096 4775 7912 40 3259 17301 20802 41 129 8396 15132 42 17825 28119 28676 43 2343 8382 28840 44 3907 18374 20939 45 1132 1290 8786 46 1481 4710 28846 47 2185 3705 26834 48 5496 15681 21854 49 12697 13407 22178 50 12788 21227 22894 51 629 2854 6232 52 2289 18227 27458 53 7593 21935 23001 54 3836 7081 12282 55 7925 18440 23135 56 497 6342 9717 57 11199 22046 30067 58 12572 28045 28990 59 1240 2023 10933 60 19566 20629 25186 61 6442 13303 28813 62 4765 10572 16180 63 552 19301 24286 64 6782 18480 21383 65 11267 12288 15758 66 771 5652 15531 67 16131 20047 25649 68 13227 23035 24450 69 4839 13467 27488 70 2352 4677 22993 71 2504 28116 29524 72 12518 17374 24267 73 1222 11859 27922 74 9660 17286 18261 75 232 11296 29978 76 9750 11165 16295 77 4894 9505 23622 78 10861 11980 14110 79 2128 15883 22836 80 6274 17243 21989 81 10866 13202 22517 82 11159 16111 21608 83 3719 18787 22100 84 1756 2020 23901 85 20913 29473 30103 86 2729 15091 26976 87 4410 8217 12963 88 5395 24564 28235 89 3859 17909 23051 90 5733 26005 29797 91 1935 3492 29773 92 11903 21380 29914 93 6091 10469 29997 94 2895 8930 15594 95 1827 10028 20070

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate R is 9/15, and M is 360, the indexes of the rows where 1 is located in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are as shown in Table 7 presented below:

TABLE 7 i Index of row where 1 is located in the 0th column of the ith column group 0 113 1557 3316 5680 6241 10407 13404 13947 14040 14353 15522 15698 16079 17363 19374 19543 20530 22833 24339 1 271 1361 6236 7006 7307 7333 12768 15441 15568 17923 18341 20321 21502 22023 23938 25351 25590 25876 25910 2 73 605 872 4008 6279 7653 10346 10799 12482 12935 13604 15909 16526 19782 20506 22804 23629 24859 25600 3 1445 1690 4304 4851 8919 9176 9252 13783 16076 16675 17274 18806 18882 20819 21958 22451 23869 23999 24177 4 1290 2337 5661 6371 8996 10102 10941 11360 12242 14918 16808 20571 23374 24046 25045 25060 25662 25783 25913 5 28 42 1926 3421 3503 8558 9453 10168 15820 17473 19571 19685 22790 23336 23367 23890 24061 25657 25680 6 0 1709 4041 4932 5968 7123 8430 9564 10596 11026 14761 19484 20762 20858 23803 24016 24795 25853 25863 7 29 1625 6500 6609 16831 18517 18568 18738 19387 20159 20544 21603 21941 24137 24269 24416 24803 25154 25395 8 55 66 871 3700 11426 13221 15001 16367 17601 18380 22796 23488 23938 25476 25635 25678 25807 25857 25872 9 1 19 5958 8548 8860 11489 16845 18450 18469 19496 20190 23173 25262 25566 25668 25679 25858 25888 25915 10 7520 7690 8855 9183 14654 16695 17121 17854 18083 18428 19633 20470 20736 21720 22335 23273 25083 258293 25403 11 48 58 410 1299 3786 10668 18523 18963 20864 22106 22308 23033 23107 23128 23990 24286 24409 24595 25802 12 12 51 3894 6539 8276 10885 11644 12777 13427 14039 15954 17078 19053 20537 22863 24521 25087 25463 25838 13 3509 8748 9581 11509 15884 16230 17583 19264 20900 21001 21310 22547 22756 22959 24768 24814 25594 25626 25880 14 21 29 69 1448 2386 4601 6626 6667 10242 13141 13852 14137 18640 19951 22449 23454 24431 25512 25814 15 18 53 7890 9934 10063 16728 19040 19809 20825 21522 21800 23582 24556 25031 25547 255692 25733 25789 25906 16 4096 4582 5766 5894 6517 100127 1282 13247 15207 17041 18958 20133 20503 22228 24332 24613 25689 25855 25883 17 0 25 819 5539 7076 7536 7695 9532 13668 150581 17683 19665 20253 21996 24136 24890 25758 25784 25807 18 34 40 44 4215 6076 7427 7965 8777 11017 15593 19542 22202 22973 23397 23423 24418 24873 25107 25644 19 1595 6216 22850 25439 20 1562 15172 19517 22362 21 7508 12879 24324 24496 22 6298 15819 16757 18721 23 11173 15175 19966 21195 24 59 13505 16941 23793 25 2267 4830 12023 20587 26 8827 9278 13072 16664 27 14419 17463 23398 25348 28 6112 16534 20423 22698 29 493 8914 21103 24799 30 6896 12761 13206 25873 31 2 1380 12322 21701 32 11600 21306 25753 25790 33 8421 13076 14271 15401 33 8421 13076 14271 15401 34 9630 14112 19017 20955 35 212 13932 21781 25824 36 5961 9110 16654 19636 37 58 5434 9936 12770 38 6575 11433 19798 39 2731 7338 20926 40 14253 18463 25404 41 21791 24805 25869 42 2 11646 15850 43 6075 8586 23819 44 18435 22093 24852 45 2103 2368 11704 46 10925 17402 18232 47 9062 25061 25674 48 18497 20853 23404 49 18606 19364 19551 50 7 1022 25543 51 6744 15481 25868 52 9081 17305 25164 53 8 23701 25883 54 9680 19955 22848 55 56 4564 19121 56 5595 15086 25892 57 3174 17127 23183 58 19397 19817 20275 59 12561 24571 25825 60 7111 9889 25865 61 1914 20189 21851 62 549 9686 25548 63 6586 20325 25906 64 3224 20710 21637 65 641 15215 25754 66 13484 23729 25818 67 2043 7493 24246 68 16860 25230 25768 69 22047 24200 247902 70 9391 18040 19499 71 7855 24336 25069 72 23834 25570 25852 73 1977 8800 25756 74 6671 21772 25859 75 3279 6710 24444 76 24099 25117 25820 77 5553 12306 25915 78 48 11107 23907 79 10832 11974 25773 80 2223 17905 25484 81 16782 17135 20446 82 475 2861 3457 83 16218 22449 24362 84 11716 22200 25897 85 8315 15009 22633 86 13 20480 25852 87 12352 18658 25687 88 3681 14794 23703 89 30 24531 25846 90 4103 22077 24107 91 23837 25622 25812 92 3627 13387 25839 93 908 5367 19388 94 0 6894 25795 95 20322 23546 25181 96 8178 25260 25437 97 2449 13244 22565 98 31 18928 22741 99 1312 5134 14838 100 6085 13937 24220 101 66 14633 25670 102 47 22512 25472 103 8867 24704 25279 104 6742 21623 22745 105 147 9948 24178 106 8522 24261 24307 107 19202 22406 24609

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of rows where 1 exists in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are defined as shown in Table 8 below.

TABLE 8 i Index of row where 1 is located in the 0th column of the ith column group 0 979 1423 4166 469 6341 8258 10334 10548 14098 14514 17051 17333 17653 17830 7990 1 2559 4025 6344 6510 9167 9728 11312 14856 17104 17721 18600 18791 19079 19697 19840 2 3243 6894 7950 10539 12042 13233 13938 14752 16449 16727 17025 18297 18796 19400 21577 3 3272 3574 6341 6722 9191 10807 10957 12531 14036 15580 16651 17007 17309 19415 19845 4 155 4598 10201 10975 11086 11296 12713 15364 15978 16395 17542 18164 18451 18612 20617 5 1128 1999 3926 4069 5558 6085 6337 8386 10693 12450 15438 16223 16370 17308 18634 6 2408 2929 3630 4357 5852 7329 8536 8695 10603 11003 14304 14937 15767 18402 21502 7 199 3066 6446 6849 8973 9536 10452 12857 13675 15913 16717 17654 19802 20115 21579 8 312 870 2095 2586 5517 6196 6757 7311 7368 13046 15384 18576 20349 21424 21587 9 985 1591 3248 359 3706 3847 6174 6276 7864 9033 13618 15675 16446 18355 18843 10 975 3774 4083 5825 6166 7218 7633 9657 10103 13052 14240 17320 18126 19544 20208 11 1795 2005 2544 3418 6148 8051 9066 9725 10676 10752 11512 15171 17523 20481 21059 12 167 315 1824 2325 2640 2868 6070 6597 7016 8109 9815 11608 16142 17912 19625 13 1298 1896 3039 4303 4690 8787 12241 13600 14478 15492 16602 17115 17913 19466 20597 14 568 3695 6045 6624 8131 8404 8590 9059 9246 11570 14336 18657 18941 19218 21506 15 228 1889 1967 2299 3011 5074 7044 7596 7689 9534 10244 10697 11691 17902 21410 16 1330 1579 1739 2234 3701 3865 5713 6677 7263 11172 12143 12765 17121 20011 21436 17 303 1668 2501 4925 5778 5985 9635 10140 10820 11779 11849 12058 15650 20426 20527 18 698 2484 3071 3219 4054 4125 5663 5939 6928 7086 8054 12173 16280 17945 19302 19 232 1619 3040 4901 7438 8135 9117 9233 10131 13321 17347 17436 18193 18586 19929 20 12 3721 6254 6609 7880 8139 10437 12262 13928 14065 14149 15032 15694 16264 18883 21 482 915 1548 1637 6687 9338 10163 11768 11970 15524 15695 17386 18787 19210 19340 22 1291 2500 4109 4511 5099 5194 10014 13165 13256 13972 15409 16113 16214 18584 20998 23 1761 4778 7444 7740 8129 8341 8931 9136 9207 10003 10678 13959 17673 18194 20990 24 3060 3522 5361 5692 6833 8342 8792 11023 11211 11548 11914 13987 15442 15541 19707 25 1322 2348 2970 5632 6349 7577 8782 9113 9267 9376 12042 12943 16680 16970 21321 26 6785 11960 21455 27 1223 15672 19550 28 5976 11335 20385 29 2818 9387 15317 30 2763 3554 18102 31 5230 11489 18997 32 5809 15779 20674 33 2620 17838 18533 34 3025 9342 9931 35 3728 5337 12142 36 2520 6666 9164 37 12892 15307 20912 38 10736 12393 16539 39 1075 2407 12853 40 4921 5411 18206 41 5955 15647 16838 42 6384 10336 19266 43 429 10421 17266 44 4880 10431 12208 45 2910 11895 12442 46 7366 18362 18772 47 4341 7903 14994 48 4564 6714 7378 49 4639 8652 18871 50 15787 18048 20246 51 3241 11079 13640 52 1559 2936 15881 53 2737 6349 10881 54 10394 16107 17073 55 8207 9043 12874 56 7805 16058 17905 57 11189 15767 17764 58 5823 12923 14316 59 11080 20390 20924 60 568 8263 17411 61 1845 3557 6562 62 2890 10936 14756 63 9031 14220 21517 64 3529 12955 15902 65 413 6750 8735 66 6784 12092 16421 67 12019 13794 15308 68 12588 15378 17676 69 8067 14589 19304 70 1244 5877 6085 71 15897 19349 19993 72 1426 2394 12264 73 3456 8931 12075 74 13342 15273 20351 75 9138 13352 20798 76 7031 7626 14081 77 4280 4507 15617 78 4170 10569 14335 79 3839 7514 16578 80 4688 12815 18782 81 4861 7858 9435 82 605 5445 12912 83 2280 4734 7311 84 6668 8128 12638 85 3733 10621 19534 86 13933 18316 19341 87 1786 3037 21566 88 2202 13239 16432 89 4882 5808 9300 90 4580 8484 16754 91 14630 17502 18269 92 6889 11119 12447 93 8162 9078 16330 94 6538 17851 18100 95 17763 19793 20816 96 2183 11907 17567 97 6640 14428 15175 98 877 12035 14081 99 1336 6468 12328 100 5948 9146 12003 101 3782 5699 12445 102 1770 7946 8244 103 7384 12639 14989 104 1469 11586 20959 105 7943 10450 15907 106 5005 8153 10035 107 17750 18826 21513 108 4725 8041 10112 109 3837 16266 17376 110 11340 17361 17512 111 1269 4611 4774 112 2322 10813 16157 113 16752 16843 18959 114 70 4325 18753 115 3165 8153 15384 116 160 8045 16823 117 14112 16724 16792 118 4291 7667 18176 119 5943 19879 20721

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 11/15, and M is 360, the indexes of rows where 1 exists in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are defined as shown in Table 9 below.

TABLE 9 i Index of row where 1 is located in the 0th column of the ith column group 0 696 989 1238 3091 3116 3738 4269 6406 7033 8048 8157 10254 12033 16456 16912 1 444 1488 6541 8626 10735 12447 13111 13706 14135 15195 15947 16453 16916 17137 17268 2 401 460 992 1145 1576 1678 2238 2320 4280 6770 10027 12486 15363 16714 17157 3 1161 3108 3727 4508 5092 5348 5582 7727 11793 12515 12917 13362 14247 16717 17205 4 542 1190 6883 7911 8349 8835 10489 11631 14195 15009 15454 15482 16632 17040 17063 5 17 487 776 880 5077 6172 9771 11446 12798 16016 16109 16171 17087 17132 17226 6 1337 3275 3462 4229 9246 10180 10845 10866 12250 13633 14482 16024 16812 17186 17241 7 15 980 2305 3674 5971 8224 11499 11752 11770 12897 14082 14836 15311 16391 17209 8 0 3926 5869 8696 9351 9391 11371 14052 14172 14636 14974 16619 16961 17033 17237 9 3033 5317 6501 8579 10598 12168 12956 14019 15392 15806 15991 16493 16690 17062 17090 10 981 1205 4400 6410 11003 13319 13405 14695 15846 16297 16492 16563 16616 16862 16953 11 1725 4276 8869 9588 14062 14486 15474 15548 16300 16432 17042 17050 17060 17175 17273 12 1807 5921 9960 10011 14305 14490 14572 15852 16054 16061 16306 16799 16833 17136 17262 13 2826 4752 6017 6540 7016 8201 14245 14419 14716 15983 16569 16652 17171 17179 17247 14 1662 2516 3345 5229 8086 9686 11456 12210 14595 15808 16011 16421 16525 17112 17195 15 2890 4821 5987 7226 8823 9869 12468 14694 15352 15805 16075 16462 17102 17251 17263 16 3751 3890 4382 5720 10281 10411 11350 12721 13121 14127 14980 15202 15335 16735 17123 17 26 30 2805 5457 6630 7188 7477 7556 11065 16608 16859 16909 16943 17030 17103 18 40 4524 5043 5566 9645 10204 10282 11696 13080 14837 15607 16274 17034 17225 17266 19 904 3157 6284 7151 7984 11712 12887 13767 15547 16099 16753 16829 17044 17250 17259 20 7 311 4876 8334 9249 11267 14072 14559 15003 15235 15686 16331 17177 17238 17253 21 4410 8066 8596 9631 10369 11249 12610 15769 16791 16960 17018 17037 17062 17165 17204 22 24 8261 9691 10138 11607 12782 12786 13424 13933 15262 15795 16476 17084 17193 17220 23 88 11622 14705 15890 24 304 2026 2638 6018 25 1163 4268 11620 17232 26 9701 11785 14463 17260 27 4118 10952 12224 17006 28 3647 10823 11521 12050 29 1717 3753 9199 11642 30 2187 14280 17220 31 14787 16903 17061 32 381 3534 4294 33 3149 6947 8323 34 12562 16724 16881 35 7289 9997 15306 36 5615 13152 17260 37 5666 16926 17027 38 4190 7798 16831 39 4778 10629 17180 40 10001 13884 15453 41 6 2237 8203 42 7831 15144 15160 43 9186 17204 17243 44 9435 17168 17237 45 42 5701 17159 46 7812 14259 15715 47 39 4513 6658 48 38 4513 6658 49 1119 4785 17182 50 5620 16521 16729 51 16 6685 17242 52 210 3452 12383 53 466 14462 16250 54 10548 12633 13962 55 1452 6005 16453 56 22 4120 13684 57 5195 11563 16522 58 5518 16705 17201 59 12233 14552 15471 60 6067 13440 17248 61 8660 8967 17061 62 8673 12176 15051 63 5959 15767 16541 64 3244 12109 12414 65 31 15913 16323 66 3270 15686 16653 67 24 7346 14675 68 12 1531 8740 69 6228 7565 16667 70 16936 17122 17162 71 4868 8451 13183 72 3714 4451 16919 73 11313 13801 17132 74 17070 17191 17242 75 1911 11201 17186 76 14 17190 17254 77 11760 16008 16832 78 14543 17033 17278 79 16129 16765 17155 80 6891 15561 17007 81 12741 14744 17116 82 8992 16661 17277 83 1861 11130 16742 84 4822 13331 16192 85 13281 14027 14989 86 38 14887 17141 87 10698 13452 15674 88 4 2539 16877 89 857 17170 17249 90 11449 11906 12807 91 285 14118 16831 92 15191 17214 17242 93 39 728 16915 94 2469 12969 15579 95 16644 17151 17164 96 2592 8280 10448 97 9236 12431 17173 98 9064 16892 17233 99 4526 16146 17038 100 31 2116 16083 101 15837 16951 17031 102 5362 8382 16618 103 6137 13199 17221 104 2841 15068 17068 105 24 3620 17003 106 9880 15718 16764 107 1784 10240 17208 108 2731 10293 10846 109 3121 8723 16598 110 8563 15662 17088 111 13 1167 14676 112 29 13850 15963 113 3654 7553 8114 114 23 4362 14865 115 4434 14741 16688 116 8362 13901 17244 117 13687 16736 17232 118 46 4229 13394 119 13169 16383 16972 120 16031 16681 16952 121 3384 9894 12580 122 9841 14414 16165 123 5013 17099 17115 124 2130 8941 17266 125 6907 15428 17241 126 16 1860 17235 127 2151 16014 16643 128 14954 15958 17222 129 3969 8419 15116 130 31 15593 16984 131 11514 16605 17255

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 12/15, and M is 360, the indexes of rows where 1 exists in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are defined as shown in Table 10 below.

TABLE 10 i Index of row where 1 is located in the 0th column of the ith column group 0 584 1472 1621 1867 3338 3568 3723 4185 5126 5889 7737 8632 8940 9725 1 221 445 590 3779 3835 6939 7743 8280 8448 8491 9367 10042 11242 12917 2 4662 4837 4900 5029 6449 6687 6751 8684 9936 11681 11811 11886 12089 12909 3 2418 3018 3647 4210 4473 7447 7502 9490 10067 11092 11139 11256 12201 12383 4 2591 2947 3349 3406 4417 4519 5176 6672 8498 8863 9201 11294 11376 12184 5 27 101 197 290 871 1727 3911 5411 6676 8701 9350 10310 10798 12439 6 1765 1897 2923 3584 3901 4048 6963 7054 7132 9165 10184 10824 11278 12669 7 2183 3740 4808 5217 5660 6375 6787 8219 8466 9037 10353 10583 11118 12762 8 73 1594 2146 2715 3501 3572 3639 3725 6959 7187 8406 10120 10507 10691 9 240 732 1215 2185 2788 2830 3499 3881 4197 4991 6425 7061 9756 10491 10 831 1568 1828 3424 4319 4516 4639 6018 9702 10203 10417 11240 11518 12458 11 2024 2970 3048 3638 3676 4152 5284 5779 5926 9426 9945 10873 11787 11837 12 1049 1218 1651 2328 3493 4363 5750 6483 7613 8782 9738 983 11744 11937 13 1193 2060 2289 2964 3478 4592 4756 6709 7162 8231 8326 11140 11908 12243 14 978 2120 2439 3338 3850 4589 6567 8745 9656 9708 10161 10542 10711 12639 15 2403 2938 3117 3247 3711 5593 5844 5932 7801 10152 10226 11498 12162 12941 16 1781 2229 2276 2533 3582 3951 5279 5774 793 9824 10920 11038 12340 12440 17 289 384 1980 2230 3464 3873 5958 8656 8942 9006 10175 11425 11745 12530 18 155 354 1090 1330 2002 2236 3559 3705 4922 5958 6576 8564 9972 12760 19 303 876 2059 2142 5244 5330 6644 7576 8614 9598 10410 10718 11033 12957 20 3449 3617 4408 4602 4727 6182 8835 8928 9372 9644 10237 10747 11655 12747 21 811 2565 2820 8677 8974 9632 11069 11548 11839 12107 12411 12695 12812 12890 22 972 4123 4943 6385 6449 7339 7477 8379 9177 9359 10074 11709 12552 12831 23 842 973 1541 2262 2905 5276 6758 7099 7894 8128 8325 8663 8875 10050 24 474 791 968 3902 4924 4965 5085 5908 6109 6329 7931 9038 9401 10568 25 1397 4461 4658 5911 6037 7127 7318 8678 8924 9000 9473 9602 10446 12692 26 1334 7571 12881 27 1393 1447 7972 28 633 1257 10597 29 4843 5102 11056 30 3294 8015 10513 31 1108 10374 10546 32 5353 7824 10111 33 3398 7674 8569 34 7719 9478 10503 35 2997 9418 9581 36 5777 6519 11229 37 1966 5214 9899 38 6 4088 5827 39 836 9248 9612 40 483 7229 7548 41 7865 8289 9804 42 2915 11098 11900 43 6180 7096 9481 44 1431 6786 8924 45 748 6757 8625 46 3312 4475 7204 47 1852 8958 11020 48 1915 2903 4006 49 6776 10886 12531 50 2594 9998 12742 51 159 2002 12079 52 853 3281 3762 53 5201 5798 6413 54 3882 6062 12047 55 4133 6775 9657 56 228 6874 11183 57 7433 10728 10864 58 7735 8073 12734 59 2844 4621 11779 60 3909 7103 12804 61 6002 9704 11060 62 5864 6856 7681 63 3652 5869 7605 64 2546 2657 4461 65 2423 4203 9111 66 244 1855 4691 67 1106 2178 6371 68 391 1617 10126 69 250 9259 10603 70 3435 4614 6924 71 1742 8045 9529 72 7667 8875 11451 73 4023 6108 6911 74 8621 10184 11650 75 6726 10861 12348 76 3228 6302 7388 77 1 1137 5358 78 381 2424 8537 79 3256 7508 10044 80 1980 2219 4569 81 2468 5699 10319 82 2803 3314 12808 83 8578 9642 11533 84 829 4585 7923 85 59 329 5575 86 1067 5709 6867 87 1175 4744 12219 88 109 2518 6756 89 2105 10626 11153 90 5192 10696 10749 91 6260 7641 8233 92 2998 3094 11214 93 3398 6466 11494 94 6574 10448 12160 95 2734 10755 12780 96 1028 7958 10825 97 8545 8602 10793 98 392 3398 11417 99 6639 9291 12571 100 1067 7919 8934 101 1064 2848 12753 102 6076 8656 12690 103 5504 6193 10171 104 1951 7156 7356 105 4389 4780 7889 106 526 4804 9141 107 1238 3648 10464 108 2587 5624 12557 109 5560 5903 11963 110 1134 2570 3297 111 10041 11583 12157 112 1263 9585 12912 113 3744 7898 10646 114 45 9074 10315 115 1051 6188 10038 116 2242 8394 12712 117 3598 9025 12651 118 2295 3540 5610 119 1914 4378 12423 120 1766 3635 12759 121 5177 9586 11143 122 943 3590 11649 123 4864 6905 10454 124 5852 6042 10421 125 6095 8285 12349 126 2070 7171 8563 127 718 12234 12716 128 512 10667 11353 129 3629 6485 7040 130 2880 8865 11466 131 4490 10220 11796 132 5440 8819 9103 133 5262 7543 12411 134 516 7779 10940 135 2515 5843 9202 136 4684 5994 10586 137 573 2270 3324 138 7870 8317 10322 139 6856 7638 12909 140 1583 7669 10781 141 8141 9085 12555 142 3903 5485 9992 143 4467 11998 12904

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 13/15, and M is 360, the indexes of rows where 1 exists in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are defined as shown in Table 11 below.

TABLE 11 i Index of row where 1 is located in the 0th column of the ith column group 0 142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125 1 2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583 2 899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602 3 21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616 4 20 1745 2838 3799 4380 4418 4645 5059 7343 8161 8302 8456 8631 5 9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632 6 494 1165 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625 7 192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632 8 11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602 9 6 2654 3554 4483 4966 5856 6795 5069 8249 8301 8497 8509 8623 10 21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611 11 335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8469 8636 12 2919 4331 4419 4735 5366 6393 6844 7193 8155 8205 8544 8586 5617 13 12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137 14 710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619 15 200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526 16 3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636 17 3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598 18 105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587 19 787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537 20 15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568 21 36 5216 5368 5616 6029 6591 8038 8057 8299 8351 8565 8578 8585 22 1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437 23 629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8512 24 11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565 25 2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614 26 5600 6591 7491 7696 27 1766 8281 8626 28 1725 2280 5120 29 1650 3445 7652 30 4312 6911 8526 31 15 1013 5892 32 2263 2546 2979 33 1545 5873 7406 34 67 726 3697 35 2860 6443 8542 36 17 911 2820 37 1561 4580 6052 38 79 5269 7134 39 22 2410 2424 40 3501 5642 8627 41 808 6950 8571 42 4099 6389 7482 43 4023 5000 7833 44 5476 5765 7917 45 1008 3194 7207 46 20 495 5411 47 1703 8388 8635 48 6 4395 4921 49 200 2053 8206 50 1089 5126 5562 51 10 4193 7720 52 1967 2151 4608 53 22 738 3513 54 3385 5066 8152 55 440 1118 8517 56 3429 6058 7716 57 5213 7519 8382 58 5564 8365 8620 59 43 3219 8603 60 4 5409 5815 61 5 6376 7654 62 4091 5224 5953 63 5348 6754 8613 64 1634 6398 6632 65 72 2058 8605 66 3492 5811 7579 67 3846 6743 8559 68 15 5933 8629 69 2133 5859 7068 70 4151 4617 8566 71 2960 8270 8410 72 2059 3517 8210 73 544 1441 6895 74 4043 7482 8592 75 294 2180 8524 76 3058 8227 8373 77 364 5756 8617 78 5383 8555 8619 79 1704 2480 4181 80 7338 7929 7990 81 2615 3905 7981 82 4298 4548 8296 83 8262 8319 8630 84 892 1893 8028 85 5694 7237 8595 86 1487 5012 5810 87 4335 8593 8624 88 3509 4531 5273 89 10 22 830 90 4161 5208 6280 91 275 7063 8634 92 4 2725 3113 93 2279 7403 8174 94 1537 3328 3930 95 2810 4939 5624 96 3 1234 7687 97 2799 7740 8616 98 22 7701 8635 99 4302 7857 7993 100 7477 7794 8592 101 9 6111 8591 102 5 8606 8628 103 347 3497 4033 104 1747 2613 8636 105 1827 5600 7042 106 580 1822 6842 107 232 7134 7783 108 4629 5000 7231 109 951 2806 4947 110 571 3474 8577 111 2437 2496 7945 112 23 5873 8162 113 12 1168 7686 114 8315 8540 8596 115 1766 2506 4733 116 929 1516 3338 117 21 1216 6555 118 782 1452 8617 119 8 6083 6087 120 667 3240 4583 121 4030 4661 5790 122 559 7122 8553 123 3202 4388 4909 124 2533 3673 8594 125 1991 3954 6206 126 6835 7900 7980 127 189 5722 8573 128 2680 4928 4998 129 243 2579 7735 130 4281 8132 8566 131 7656 7671 8609 132 1116 2291 4166 133 21 388 8021 134 6 1123 8369 135 311 4918 8511 136 0 3248 6290 137 13 6762 7172 138 4209 5632 7563 139 49 127 8074 140 581 1735 4075 141 0 2235 5470 142 2178 5820 6179 143 16 3575 6054 144 1095 4564 6458 145 9 1581 5953 146 2537 6469 8552 147 14 3874 4844 148 0 3269 3551 149 2114 7372 7926 150 1575 2388 4057 151 3232 4042 6663 152 9 401 583 153 13 4100 6584 154 2299 4190 4410 155 21 3670 4979

According to an exemplary embodiment, even when the order of numbers, i.e., indexes, in a sequence corresponding to the i^(th) column group of the parity check matrix 200 as shown in the above-described Tables 4 to 11 is changed, the changed parity check matrix is a parity check matrix used for the same LDPC code. Therefore, a case in which the order of numbers in the sequence corresponding to the i^(th) column group in Tables 4 to 11 is changed is covered by the inventive concept.

According to an exemplary embodiment, even when one sequence corresponding to one column group is changed and another sequence corresponding to another column group are changed to each other in Tables 4 to 11, cycle characteristics on a graph of the LDPC code and algebraic characteristics such as degree distribution are not changed. Therefore, a case in which the arrangement order of the sequences shown in Tables 4 to 11 is changed is also covered by the inventive concept.

In addition, even when a multiple of Q_(ldpc) is equally added to all numbers, i.e., indexes, corresponding to a certain column group in Tables 4 to 11, the cycle characteristics on the graph of the LDPC code or the algebraic characteristics such as degree distribution are not changed. Therefore, a result of equally adding a multiple of Q_(ldpc) to the sequences shown in Tables 4 to 11 is also covered by the inventive concept. However, it should be noted that, when the resulting value obtained by adding a multiple of Q_(ldpc) to a given sequence is greater than or equal to (N_(ldpc)−K_(ldpc)), a value obtained by applying a modulo operation for (N_(ldpc)−K_(ldpc)) to the resulting value should be applied instead.

Once positions of the rows where 1 exists in the 0^(th) column of the i^(th) column group of the information word submatrix 210 are defined as shown in Tables 4 to 11, positions of rows where 1 exists in another column of each column group may be defined since the positions of the rows where 1 exists in the 0^(th) column are cyclic-shifted by Q_(ldpc) in the next column.

For example, in the case of Table 4, in the 0^(th) column of the 0^(th) column group of the information word submatrix 210, 1 exists in the 1606^(th) row, 3402^(th) row, 4961^(st) row, . . . .

In this case, since Q_(ldpc)(N_(ldpc)−K_(ldpc))/M=(64800−25920)/360=108, the indexes of the rows where 1 is located in the 1^(st) column of the 0^(th) column group may be 1714(=1606+108), 510(=3402+108), 5069(=4961+108), . . . , and the indexes of the rows where 1 is located in the 2^(nd) column of the 0^(th) column group may be 1822(=1714+108), 3618(=3510+108), 5177(=5069+108).

In the above-described method, the indexes of the rows where 1 is located in all rows of each column group may be defined.

The parity submatrix 220 of the parity check matrix 200 shown in FIG. 2 may be defined as follows:

The parity submatrix 220 includes N_(ldpc)−K_(ldpc) number of columns (that is, K_(ldpc) ^(th) column to (N_(ldpc)−1)^(th) column), and has a dual diagonal or staircase configuration. Accordingly, the degree of columns except the last column (that is, (N_(ldpc)−1)^(th) column) from among the columns included in the parity submatrix 220 is 2, and the degree of the last column is 1.

As a result, the information word submatrix 210 of the parity check matrix 200 may be defined by Tables 4 to 11, and the parity submatrix 220 may have a dual diagonal configuration.

When the columns and rows of the parity check matrix 200 shown in FIG. 2 are permutated based on Equation 4 and Equation 5, the parity check matrix shown in FIG. 2 may be changed to a parity check matrix 300 shown in FIG. 3.

Q _(ldpc) ·i+j

M·j+i (0≦i<M,0≦j<Q _(ldpc))  (4)

K _(ldpc) +Q _(ldpc) ·k+l

K _(ldpc) +M·l+k (0≦k<M,0≦l<Q _(ldpc))  (5)

The method for permutating based on Equation 4 and Equation 5 will be explained below. Since row permutation and column permutation apply the same principle, the row permutation will be explained by the way of an example.

In the case of the row permutation, regarding the X^(th) row, i and j satisfying X=Q_(ldpc)×i+j are calculated and the X^(th) row is permutated by assigning the calculated i and j to M×j+i. For example, regarding the 7^(th) row, i and j satisfying 7=2×i+j are 3 and 1, respectively. Therefore, the 7^(th) row is permutated to the 13^(th) row (10×1+3=13).

When the row permutation and the column permutation are performed in the above-described method, the parity check matrix of FIG. 2 may be converted into the parity check matrix of FIG. 3.

Referring to FIG. 3, the parity check matrix 300 is divided into a plurality of partial blocks, and a quasi-cyclic matrix of M×M corresponds to each partial block.

Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is formed of matrix units of M×M. That is, the submatrices of M×M are arranged in the plurality of partial blocks, constituting the parity check matrix 300.

Since the parity check matrix 300 is formed of the quasi-cyclic matrices of M×M, M number of columns may be referred to as a column block and M number of rows may be referred to as a row block. Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is formed of N_(qc) _(—) _(column)=N_(ldpc)/M number of column blocks and N_(qc) _(—) _(row)=N_(parity)/M number of row blocks.

Hereinafter, the submatrix of M×M will be explained.

First, the (N_(qc) _(—) _(column)−1) column block of the 0^(th) row block has a form shown in Equation 6 presented below:

$\begin{matrix} {A = \begin{bmatrix} 0 & 0 & \ldots & 0 & 0 \\ 1 & 0 & \ldots & 0 & 0 \\ 0 & 1 & \ldots & 0 & 0 \\ \vdots & \vdots & \vdots & \vdots & \vdots \\ 0 & 0 & \ldots & 1 & 0 \end{bmatrix}} & (6) \end{matrix}$

As described above, A 330 is an M×M matrix, values of the 0^(th) row and the (M−1)^(th) column are all “0”, and, regarding 0≦i≦(M−2), the (i+1)^(th) row of the i^(th) column is “1” and the other values are “0”.

Second, regarding 0≦i≦(N_(ldpc)−K_(ldpc))/M−1 in the parity submatrix 320, the i^(th) row block of the (K_(ldpc)/M+i)^(th) column block is configured by a unit matrix I_(M×M) 340. In addition, regarding 0≦i≦(N_(ldpc)−K_(ldpc))/M−2, the (i+1)^(th) row block of the (K_(ldpc)/M+i)^(th) column block is configured by a unit matrix I_(M×M) 340.

Third, a block 350 constituting the information word submatrix 310 may have a cyclic-shifted format of a cyclic matrix P, P^(a) ^(ij) , or an added format of the cyclic-shifted matrix P^(a) ^(ij) of the cyclic matrix P (or an overlapping format).

For example, a format in which the cyclic matrix P is cyclic-shifted to the right by 1 may be expressed by Equation 7 presented below:

$\begin{matrix} {P = \begin{bmatrix} 0 & 1 & 0 & \; & 0 \\ 0 & 0 & 1 & \ldots & 0 \\ \vdots & \vdots & \vdots & \; & \vdots \\ 0 & 0 & 0 & \ldots & 1 \\ 1 & 0 & 0 & \; & 0 \end{bmatrix}} & (7) \end{matrix}$

The cyclic matrix P is a square matrix having an M×M size and is a matrix in which a weight of each of M number of rows is 1 and a weight of each of M number of columns is 1. When a_(ij) is 0, the cyclic matrix P, that is, P⁰ indicates a unit matrix I_(M×M), and when a_(ij) is ∞, P^(∞) is a zero matrix.

A submatrix existing where the i^(th) row block and the j^(th) column block intersect in the parity check matrix 300 of FIG. 3 may be P^(a) ^(ij) . Accordingly, i and j indicate the number of row blocks and the number of column blocks in the partial blocks corresponding to the information word. Accordingly, in the parity check matrix 300, the total number of columns is N_(ldpc)=M×N_(qc) _(—) _(column), and the total number of rows is N_(parity)=M×N_(qc) _(—) _(row). That is, the parity check matrix 300 is formed of N_(qc) _(—) _(column) number of column blocks and N_(qc) _(—) _(row) number of row blocks.

Referring back to FIG. 1, the encoder 110 may perform the LDPC encoding by using various code rates such as 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, etc. In addition, the encoder 110 may generate an LDPC codeword having various lengths such as 16200, 64800, etc., based on the length of the information word bits and the code rate.

In this case, the encoder 110 may perform the LDPC encoding by using the parity check matrix, and the parity check matrix is configured as shown in FIGS. 2 and 3.

In addition, the encoder 110 may perform Bose, Chaudhuri, Hocquenghem (BCH) encoding as well as LDPC encoding. To achieve this, the encoder 110 may further include a BCH encoder (not shown) to perform BCH encoding.

In this case, the encoder 110 may perform encoding in an order of BCH encoding and LDPC encoding. Specifically, the encoder 110 may add BCH parity bits to input bits by performing BCH encoding and LDPC-encodes the bits to which the BCH parity bits are added into information word bits, thereby generating the LDPC codeword.

The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoder 110, and interleaves the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 may interleave the LDPC codeword such that a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword (that is, a plurality of bit groups or a plurality of blocks) is mapped onto a predetermined bit of a modulation symbol. Accordingly, the modulator 130 may map a bit included in a predetermined group from among the plurality of groups of the LDPC codeword onto a predetermined bit of the modulation symbol.

Hereinafter, the interleaver 120 will be explained in detail with reference to FIGS. 4 to 11.

According to an exemplary embodiment, the interleaver 120 may interleave the LDPC codeword in a method described below such that a bit included in a predetermined group from among a plurality of groups constituting the interleaved LDPC codeword is mapped onto a predetermined bit in a modulation symbol. A detailed description thereof is provided with reference to FIG. 4.

FIG. 4 is a block diagram to illustrate a configuration of an interleaver according to exemplary embodiment. Referring to FIG. 4, the interleaver 120 includes a parity interleaver 121, a group interleaver (or a group-wise interleaver 122), a group twist interleaver 123 and a block interleaver 124.

The parity interleaver 121 interleaves parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the configuration of FIG. 2, the parity interleaver 121 may interleave only the parity bits of the LDPC codeword by using Equations 8 presented below:

u _(i) =c _(i) for 0≦i<K _(ldpc), and

u _(K) _(ldpc) _(+M·t+s) =C _(K) _(ldpc) _(+Q) _(ldpc) _(·s+t) for 0≦s<M, 0≦t<Q _(ldpc)  (8),

where M is an interval at which a pattern of a column group, which includes a plurality of columns, is repeated in the information word submatrix 210, that is, the number of columns included in a column group (for example, M=360), and Q_(ldpc) is a size by which each column is cyclic-shifted in the information word submatrix 210. That is, the parity interleaver 121 performs parity interleaving with respect to the LDPC codeword c=(c₀, c₁, . . . , C_(N) _(ldpc) ⁻¹), and outputs U=(u₀, u₁, . . . , U_(N) _(ldpc) ⁻¹).

When the LDPC codeword encoded based on the parity check matrix 200 of FIG. 2 is parity-interleaved based on Equations 8, the parity-interleaved LDPC codeword is the same as the LDPC codeword encoded by the parity check matrix 300 of FIG. 3. Accordingly, when the LDPC codeword is generated based on the parity check matrix 300 of FIG. 3, the parity interleaver 121 may be omitted.

The LDPC codeword parity-interleaved after having been encoded based on the parity check matrix 200 of FIG. 2, or the LDPC codeword encoded based on the parity check matrix having the format of FIG. 3 may be characterized in that a predetermined number of continuous bits of the LDPC codeword have similar decoding characteristics (cycle distribution, a degree of a column, etc.).

For example, the LDPC codeword may have the same characteristics on the basis of M number of continuous bits. Herein, M is an interval at which a pattern of a column group is repeated in the information word submatrix and, for example, may be 360.

Specifically, a product of the LDPC codeword bits and the parity check matrix should be “0”. This means that a sum of products of the i^(th) LDPC codeword bit, c_(i) (i=0, 1, . . . , N_(ldpc)−1) and the i^(th) column of the parity check matrix should be a “0” vector. Accordingly, the i^(th) LDPC codeword bit may be regarded as corresponding to the i^(th) column of the parity check matrix.

In the case of the parity check matrix of FIG. 2, M number of columns in the information word submatrix 210 belong to the same group and the information word submatrix 210 has the same characteristics on the basis of a column group (for example, the columns belonging to the same column group have the same degree distribution and the same cycle characteristic).

In this case, since M number of continuous bits in the information word bits correspond to the same column group of the information word submatrix 210, the information word bits may be formed of M number of continuous bits having the same codeword characteristics. When the parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may be formed of M number of continuous bits having the same codeword characteristics.

In addition, in the case of the parity check matrix 300 of FIG. 3, since the information word submatrix 310 and the parity submatrix 320 of the parity check matrix 300 have the same characteristics on the basis of a column group including M number of columns due to the row and column permutation, the information word bits and the parity bits of the LDPC codeword encoded based on the parity check matrix 300 are formed of M number of continuous bits of the same codeword characteristics.

Herein, the row permutation does not influence the cycle characteristic or algebraic characteristic of the LDPC codeword such as a degree distribution, a minimum distance, etc. since the row permutation is just to rearrange the order of rows in the parity check matrix. In addition, since the column permutation is performed for the parity submatrix 320 to correspond to parity interleaving performed in the parity interleaver 121, the parity bits of the LDPC codeword encoded by the parity check matrix 300 of FIG. 3 are formed of M number of continuous bits like the parity bits of the LDPC codeword encoded by the parity check matrix 200 of FIG. 2.

Accordingly, the bits constituting an LDPC codeword may have the same characteristics on the basis of M number of continuous bits, according to the present exemplary embodiment.

The group interleaver 122 may divide the LDPC codeword into a plurality of groups and rearrange the order of the plurality of groups or may divide the parity-interleaved LDPC codeword into a plurality of groups and rearrange the order of the plurality of groups. That is, the group interleaver 122 interleaves the plurality of groups in group units.

To achieve this, the group interleaver 122 divides the parity-interleaved LDPC codeword into a plurality of groups by using Equation 9 or Equation 10 presented below.

$\begin{matrix} {X_{j} = {{\left\{ {{\left. u_{k} \middle| j \right. = \left\lfloor \frac{k}{360} \right\rfloor},{0 \leq k < N_{ldpc}}} \right\} \mspace{14mu} {for}\mspace{14mu} 0} \leq j < N_{group}}} & (9) \\ {{X_{j} = \left\{ {\left. u_{k} \middle| {{360 \times j} \leq k < {360 \times \left( {j + 1} \right)}} \right.,{0 \leq k < N_{lpdc}}} \right\}}\; {{{for}\mspace{14mu} 0} \leq j < N_{group}}} & (10) \end{matrix}$

where N_(group) is the total number of groups, X_(j) is the j^(th) group, and u_(k) is the k^(th) LDPC codeword bit input to the group interleaver 122. In addition,

$\left\lfloor \frac{k}{360} \right\rfloor$

is the largest integer below k/360.

Since 360 in these equations indicates an example of the interval M at which the pattern of a column group is repeated in the information word submatrix, 360 in these equations can be changed to M.

The LDPC codeword which is divided into the plurality of groups may be as shown in FIG. 5.

Referring to FIG. 5, the LDPC codeword is divided into the plurality of groups and each group is formed of M number of continuous bits. When M is 360, each of the plurality of groups may be formed of 360 bits. Accordingly, the groups may be formed of bits corresponding to the column groups of the parity check matrix.

Specifically, since the LDPC codeword is divided by M number of continuous bits, K_(ldpc) number of information word bits are divided into (K_(ldpc)/M) number of groups and N_(ldpc)−K_(ldpc) number of parity bits are divided into (N_(ldpc)−K_(ldpc))/M number of groups. Accordingly, the LDPC codeword may be divided into (N_(ldpc)/M) number of groups in total.

For example, when M=360 and the length N_(ldpc) of the LDPC codeword is 64800, the number of groups N_(groups) is 180, and, when the length N_(ldpc) of the LDPC codeword is 16200, the number of groups N_(group) is 45.

As described above, the group interleaver 122 divides the LDPC codeword such that M number of continuous bits are included in a same group since the LDPC codeword has the same codeword characteristics on the basis of M number of continuous bits. Accordingly, when the LDPC codeword is grouped by M number of continuous bits, the bits having the same codeword characteristics belong to the same group.

In the above-described example, the number of bits constituting each group is M. However, this is merely an example and the number of bits constituting each group is variable.

For example, the number of bits constituting each group may be an aliquot part of M. That is, the number of bits constituting each group may be an aliquot part of the number of columns constituting a column group of the information word submatrix of the parity check matrix. In this case, each group may be formed of aliquot part of M number of bits. For example, when the number of columns constituting a column group of the information word submatrix is 360, that is, M=360, the group interleaver 122 may divide the LDPC codeword into a plurality of groups such that the number of bits constituting each group is one of the aliquot parts of 360.

Hereinafter, the case in which the number of bits constituting a group is M will be explained for convenience of explanation.

Thereafter, the group interleaver 122 interleaves the LDPC codeword in group units. That is, the group interleaver 122 changes positions of the plurality of groups constituting the LDPC codeword and rearranges the order of the plurality of groups constituting the LDPC codeword.

In this case, the group interleaver 122 may rearrange the order of the plurality of groups by using Equation 11 presented below:

Y _(j) =X _(π(j)) (0≦j<N _(group))  (11),

where X_(j) is the j^(th) group before group interleaving, and Y_(j) is the j^(th) group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a code rate and a modulation method.

Accordingly, X_(π(j)) is a π(j)^(th) group before group interleaving, and Equation 11 means that the pre-interleaving π(j)^(th) group is interleaved into the j^(th) group.

According to an exemplary embodiment, an example of π(j) may be defined as in Tables 12 to 14 presented below.

In this case, π(j) is defined according to a length of an LDPC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate. Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in group units based on π(j) satisfying the corresponding length of the LDPC codeword and code rate.

For example, when the encoder 110 performs LDPC encoding at a code rate of 10/15 to generate an LDPC codeword of a length of 16200, the group interleaver 122 may perform interleaving by using π(j) which is defined according to the length of the LDPC codeword of 16200 and the code rate of 10/15 in tables 12 to 14 presented below.

For example, when the length of the LDPC codeword is 16200, the code rate is 10/15, and the modulation method is 16-Quadrature Amplitude Modulation (QAM), the group interleaver 122 may perform interleaving by using π(j) defined as in table 12.

An example of π(j) is as follows:

For example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 6/15, 7/15, 8/15 and 9/15, and the modulation method is 16-QAM, π(j) may be defined as in Table 12 presented below:

TABLE 12 Order of bits group to be block interleaved □ (j) (0 ≦ j < 180) Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 6/15, 3 45 175 151 17 155 42 115 173 163 83 33 171 142 7 153 31 38 47 7/15, 5 13 129 61 25 109 85 125 141 81 77 65 105 9 133 177 97 69 157 8/15, 56 4 44 164 68 60 24 20 88 92 132 152 36 160 16 41 156 32 165 9/15 108 52 113 144 12 101 112 80 1 28 116 48 72 176 148 30 14 154 82 29 34 62 167 78 66 74 18 57 50 53 110 137 22 161 122 73 98 169 90 179 158 87 10 51 150 143 134 39 162 127 146 135 170 21 139 128 126 123 114 159 100 121 102 111 0 119 138 75 166 120 93 46 63 96 147 106 91 145 136 23 54 43 8 96 71 117 174 124 131 178 67 84 6 49 95 2 40 59 86 99 168 37 103 130 27 172 55 58 107 76 89 35 70 79 64 118 19 149 140 15 26 11 104

In the case of Table 12, Equation 11 may be expressed as Y₀=X_(π(0))=X₃, Y₁=X_(π(1))=X₄₅, Y₂=X_(π(2))=X₁₇₅, . . . , Y₁₇₈=X_(π(178))=X₁₁, and Y₁₇₉=X_(π(179))=X₁₀₄. Accordingly, the group interleaver 122 may rearrange the order of the plurality of groups by changing the 3^(th) group to the 0^(th) group, the 45^(th) group to the 1^(st) group, the 175^(th) group to the 2^(nd) group, . . . , the 11^(th) group to the 178th group, and the 104^(th) group to the 179^(th) group.

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 10/15, 11/15, 12/15 and 13/15, and the modulation method is 16-QAM, π(j) may be defined as in Table 13 presented below:

TABLE 13 Order of bits group to be block interleaved □ (j) (0 ≦ j < 180) Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 10/15, 91 161 112 113 146 143 19 173 26 77 85 95 158 41 136 29 38 59 115 11/15, 17 46 53 104 152 108 24 144 148 130 82 111 49 168 147 176 103 21 78 12/15, 96 67 69 132 117 12 1 87 84 61 51 156 142 75 127 102 3 44 169 13/15 15 138 124 165 25 72 159 121 0 171 175 150 57 139 48 106 39 97 153 42 7 105 114 55 116 93 13 63 30 37 99 126 79 81 120 151 27 54 109 135 174 145 33 60 31 129 66 163 45 68 18 9 73 6 177 133 36 141 157 90 123 43 58 107 16 64 34 131 172 160 86 178 94 88 40 62 122 98 140 56 89 80 32 110 74 20 164 149 2 14 47 152 170 155 50 134 125 92 128 11 154 5 76 179 70 71 52 119 118 23 4 65 35 100 101 22 167 166 137 28 83 10 8

In the case of Table 13, Equation 11 may be expressed as Y₀=X_(π(0))=X₉₁, Y₁=X_(π(1))=X₁₆₁, Y₂=X_(π(2))=X₁₁₂, . . . , Y₁₇₈=X_(π(178))=X₁₀, and Y₁₇₉=X_(π(179))=X₈. Accordingly, the group interleaver 122 may rearrange the order of the plurality of groups by changing the 91^(th) group to the 0^(th) group, the 161th group to the 1^(st) group, the 112nd group to the 2^(nd) group, . . . , the 10th group to the 178^(th) group, and the 8^(th) group to the 179^(th) group.

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 6/15, 7/15, 8/15 and 9/15, and the modulation method is 256-QAM, π(j) may be defined as in Table 14 presented below.

TABLE 14 Order of bits group to be block interleaved π(j) (0 ≦ j < 180) Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 6/15, 9 6 160 78 1 35 102 104 86 145 111 58 166 151 92 2 124 24 117 7/15, 19 168 79 122 32 139 42 40 105 100 144 115 154 136 97 155 24 41 138 8/15, 128 89 50 80 49 26 64 75 169 146 0 33 98 72 59 120 173 96 43 9/15 129 48 10 147 8 25 56 83 15 57 114 112 90 152 11 174 29 110 143 5 38 85 70 47 133 94 53 99 162 27 170 163 57 131 34 107 66 171 130 65 3 17 37 121 18 113 51 153 101 81 123 4 21 46 55 20 88 15 108 165 156 87 137 12 127 68 69 82 159 76 54 157 119 140 93 106 67 95 164 141 150 23 172 91 71 61 126 60 103 149 84 118 39 77 115 22 28 63 45 44 151 134 52 175 142 148 167 109 31 156 14 79 36 125 135 172 30 7 13 179 178 177 175

In the case of Table 14, Equation 11 may be expressed as Y₀=X_(π(0))=X₉, Y₁=X_(π(1))=X₆, Y₂=X_(π(2))=X₁₆₀, . . . , Y₁₇₈=X_(π(178))=X₁₇₇, Y₁₇₉=X_(π(179))=X₁₇₆. Accordingly, the group interleaver 122 may rearrange the order of the plurality of groups by changing the 9^(th) group to the 0^(th) group, the 6^(th) group to the 1^(st) group, the 160^(st) group to the 2^(nd) group, . . . , the 177^(th) group to the 178^(th) group, and the 176^(th) group to the 179th group.

In another example, when the length N_(ldpc) of the LDPC codeword is 64800, the code rate is 10/15, 11/15, 12/15 and 13/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 15 presented below:

TABLE 15 Order of bits group to be block interleaved □ (j) (0 ≦ j < 180) Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 10/15, 90 28 61 112 9 160 103 148 131 104 50 49 42 161 56 110 68 53 151 11/15, 175 179 170 38 114 172 145 47 93 174 166 71 2 155 40 123 87 34 121 12/15, 152 65 140 143 24 32 51 96 13 100 35 52 91 147 153 0 124 12 36 13/15 111 73 75 120 72 97 141 33 134 142 70 105 83 31 76 62 80 154 163 1 15 82 77 20 74 113 11 106 22 150 85 133 101 144 122 30 25 173 127 41 64 92 130 63 55 102 21 86 3 10 44 132 171 125 43 60 57 162 164 81 176 23 95 84 17 5 6 4 37 115 116 94 165 137 14 39 146 98 167 59 46 128 117 119 88 66 159 67 16 177 45 156 27 26 157 54 126 7 136 8 149 58 109 138 99 78 89 48 139 178 107 29 18 129 118 69 168 169 158 79 108 19 135

In the case of Table 15, Equation 11 may be expressed as Y₀=X_(π(0))=X₉₀, Y₁=X_(π(1))=X₂₈, Y₂=X_(π(2))=X₆₁, . . . , Y₁₇₈=X_(π(178))=X₁₉, Y₁₇₉=X_(π(179))=X₁₃₅. Accordingly, the group interleaver 122 may rearrange the order of the plurality of groups by changing the 90^(th) group to the 0^(th) group, the 28^(th) group to the 1^(st) group, the 61^(th) group to the 2^(nd) group, . . . , the 19^(th) group to the 135^(th) group, and the 135^(th) group to the 179^(th) group.

As described above, the group interleaver 122 may rearrange the order of the plurality of groups by using Equation 11 and Tables 12 to 15.

On the other hand, since the order of the groups constituting the LDPC codeword is rearranged by the group interleaver 122, and then the groups are block-interleaved by the block interleaver 124, which will be described below, “Order of bits groups to be block interleaved” is set forth in Tables 12 to 15 in relation to π(j).

The LDPC codeword which is group-interleaved in the above-described method is illustrated in FIG. 6. Comparing the LDPC codeword of FIG. 6 and the LDPC codeword of FIG. 5 before group interleaving, it can be seen that the order of the plurality of groups constituting the LDPC codeword is rearranged.

That is, as shown in FIGS. 5 and 6, the groups of the LDPC codeword are arranged in order of group X₀, group X₁, . . . , group X_(Ngroup-1) before being group-interleaved, and are arranged in an order of group Y₀, group Y₁, . . . , group Y_(Ngroup-1) after being group-interleaved. In this case, the order of arranging the groups by the group interleaving may be determined based on Tables 12 to 15.

The group twist interleaver 123 interleaves bits in a same group. That is, the group twist interleaver 123 may rearrange the order of the bits in the same group by changing the order of the bits in the same group.

In this case, the group twist interleaver 123 may rearrange the order of the bits in the same group by cyclic-shifting a predetermined number of bits from among the bits in the same group.

For example, as shown in FIG. 7, the group twist interleaver 123 may cyclic-shift bits included in the group Y₁ to the right by 1 bit. In this case, the bits located in the 0^(th) position, the 1^(st) position, the 2^(nd) position, . . . , the 358^(th) position, and the 359^(th) position in the group Y₁ as shown in FIG. 7 are cyclic-shifted to the right by 1 bit. As a result, the bit located in the 359^(th) position before being cyclic-shifted is located in the front of the group Y₁ and the bits located in the 0^(th) position, the 1^(st) position, the 2^(nd) position, . . . , the 358^(th) position before being cyclic-shifted are shifted to the right serially by 1 bit and located.

In addition, the group twist interleaver 123 may rearrange the order of bits in each group by cyclic-shifting a different number of bits in each group.

For example, the group twist interleaver 123 may cyclic-shift the bits included in the group Y₁ to the right by 1 bit, and may cyclic-shift the bits included in the group Y₂ to the right by 3 bits.

However, the above-described group twist interleaver 123 may be omitted according to circumstances.

In addition, the group twist interleaver 123 is placed after the group interleaver 122 in the above-described example. However, this is merely an example. That is, the group twist interleaver 123 changes only the order of bits in a certain group and does not change the order of the groups. Therefore, the group twist interleaver 123 may be placed before the group interleaver 122.

The block interleaver 124 interleaves the plurality of groups the order of which has been rearranged.

Specifically, the block interleaver 124 is formed of a plurality of columns including a plurality of rows, respectively, and may divide each of the plurality of columns into a first part and a second part and perform a plurality of groups constituting the LDPC codeword.

In this case, the block interleaver 124 may interleave the plurality of groups the order of which has been rearranged by the group interleaver 122.

Herein, the number of groups which are interleaved in group units may be determined by at least one of the number of rows and columns constituting the block interleaver 124, the number of groups and the number of bits included in each group. In other words, the block interleaver 124 may determine the groups which are to be interleaved in group units considering at least one of the number of rows and columns constituting the block interleaver 124, the number of groups and the number of bits included in each group, interleave the corresponding groups in group units, and divide and interleave the remaining groups. For example, the block interleaver 124 may interleave at least part of the plurality of groups in group units using the first part, and divide and interleave the remaining groups using the second part.

Meanwhile, interleaving groups in group units means that the bits included in the same group are written in the same column. In other words, the block interleaver 124, in case of groups which are interleaved in group units, may not divide the bits included in the same groups and write the bits in the same column, and in case of groups which are not interleaved in group units, may divide the bits in the groups and write the bits in different columns.

Accordingly, in all groups interleaved by the first part, the bits included in the same group are written and interleaved in the same column of the first part, and in at least one group interleaved by the second part, the bits are divided and written in at least two columns.

The specific interleaving method will be described later.

Meanwhile, the group twist interleaver 123 changes only the order of bits in the same group and does not change the order of groups by interleaving. Accordingly, the order of the groups to be block-interleaved by the block interleaver 124, that is, the order of the groups to be input to the block interleaver 124, may be determined by the group interleaver 122. Specifically, the order of the groups to be block-interleaved by the block interleaver 124 may be determined by π(j) defined in Tables 12 to 15.

As described above, the block interleaver 124 may be formed of a plurality of columns each including a plurality of rows, and may divide the plurality of columns into at least two parts and interleave an LDPC codeword.

For example, the block interleaver 124 may divide each of the plurality of columns into the first part and the second part, and may interleave a plurality of groups constituting the LDPC codeword.

In this case, the block interleaver 124 may divide each of the plurality of columns into N number of parts (N is an integer greater than or equal to 2) according to whether the number of groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, and may perform interleaving.

When the number of groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124, the block interleaver 124 may interleave the plurality of groups constituting the LDPC codeword in group units without dividing each of the plurality of columns into parts.

Specifically, the block interleaver 124 may interleave by writing the plurality of groups of the LDPC codeword on each of the columns in group units in a column direction, and reading each row of the plurality of columns in which the plurality of groups are written in group units in a row direction.

In this case, the block interleaver 124 may interleave by writing bits included in a predetermined number of groups which corresponds to a quotient obtained by dividing the number of groups of the LDPC codeword by the number of columns of the block interleaver 124 on each of the plurality of columns serially in a column direction, and reading each row of the plurality of columns in which the bits are written in a row direction.

Hereinafter, the group located in the j^(th) position after being interleaved by the group interleaver 122 will be referred to as group Y_(j).

For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R₁ number of rows. In addition, it is assumed that the LDPC codeword is formed of Y_(group) number of groups and the number of groups Y_(group) is a multiple of C.

In this case, the quotient obtained by dividing Y_(group) number of groups constituting the LDPC codeword by C number of columns constituting the block interleaver 124 and thus, the block interleaver 124 may interleave by writing Y_(group)/C number of groups on each column serially in a column direction and reading bits written on each column in a row direction.

For example, as shown in FIG. 8, the block interleaver 124 writes bits included in group Y₀, group Y₁, . . . , group Y_(p−1) in the 1^(st) column from the 1^(st) row to the R₁ ^(th) row, writes bits included in group Y_(p), group Y_(p+1), . . . , group Y_(q−1) in the 2nd column from the 1^(st) row to the R₁ ^(th) row, . . . , and writes bits included in group Y_(z), Y_(z+1), . . . , group Y_(Ngroup-1) in the column C from the 1^(st) row to the R₁ ^(th) row. The block interleaver 124 may read the bits written in each row of the plurality of columns in a row direction.

Accordingly, the block interleaver 124 interleaves all groups constituting the LDPC codeword in group units.

However, when the number of groups of the LDPC codeword is not an integer multiple of the number of columns of the block interleaver 124, the block interleaver 124 may interleave a part of the plurality of groups of the LDPC codeword in group units by dividing each column into 2 parts, and divide and interleave the remaining groups. In this case, the bits included in the remaining groups, that is, the bits included in the number of groups which correspond to the remainder when the number of groups constituting the LDPC codeword is divided by the number of columns are not interleaved in group units, but interleaved by being divided according to the number of columns.

Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.

In this case, the block interleaver 124 may divide the plurality of columns into a first part (part 1) and a second part (part 2) based on the number of columns of the block interleaver 124, the number of groups of the LDPC codeword, and the number of bits of each of the plurality of groups.

Here, each of the plurality of groups may be formed of 360 bits. In addition, the number of groups of the LDPC codeword is determined based on the length of the LDPC codeword and the bits included in each group. For example, when an LDPC codeword in the length of 16200 is divided such that each group has 360 bits, the LDPC codeword is divided into 45 groups. Alternatively, when an LDPC codeword in the length of 64800 is divided such that each group has 360 bits, the LDPC codeword may be divided into 180 groups. Further, the number of columns constituting the block interleaver 124 may be determined according to a modulation method. This will be explained in detail below.

Accordingly, the number of rows constituting each of the first part and the second part may be determined based on the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of groups.

Specifically, in each of the plurality of columns, the first part may be formed of as many rows as the number of of bits included in at least one group which can be written in each column in group units from among the plurality of groups of the LDPC codeword, according to the number of columns constituting the block interleaver 124, the number of groups constituting the LDPC codeword, and the number of bits constituting each group.

In each of the plurality of columns, the second part may be formed of rows excluding as many rows as the number of bits included in at least some groups which can be written in each of the plurality of columns in group units. Specifically, the number rows of the second part may be the same value as a quotient when the number of bits included in all bit groups excluding groups corresponding to the first part is divided by the number of columns constituting the block interleaver 124. In other words, the number of rows of the second part may be the same value as a quotient when the number of bits included in the remaining groups which are not written in the first part from among groups constituting the LDPC codeword is divided by the number of columns.

That is, the block interleaver 124 may divide each of the plurality of columns into the first part including as many rows as the number of bits included in groups which can be written in each column in group units, and the second part including the other rows.

Accordingly, the first part may be formed of as many rows as the number of bits included in groups, that is, as many rows as an integer multiple of M. However, since the number of codeword bits constituting each group may be an aliquot part of M as described above, the first part may be formed of as many rows as an integer multiple of the number of bits constituting each group.

In this case, the block interleaver 124 may interleave by writing and reading the LDPC codeword in the first part and the second part in the same method.

Specifically, the block interleaver 124 may interleave by writing the LDPC codeword in the plurality of columns constituting each of the first part and the second part in a column direction, and reading the plurality of columns constituting the first part and the second part in which the LDPC codeword is written in a row direction.

That is, the block interleaver 124 may interleave by writing the bits included in at least some groups which can be written in each of the plurality of columns in group units in each of the plurality of columns of the first serially, dividing the bits included in the other groups except the at least some groups and writing in each of the plurality of columns of the second part in a column direction, and reading the bits written in each of the plurality of columns constituting each of the first part and the second part in a row direction.

In this case, the block interleaver 124 may interleave by dividing the other groups except the at least some groups from among the plurality of groups based on the number of columns constituting the block interleaver 124.

Specifically, the block interleaver 124 may interleave by dividing the bits included in the other groups by the number of a plurality of columns, writing each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and reading the plurality of columns constituting the second part, where the divided bits are written, in a row direction.

That is, the block interleaver 124 may divide the bits included in the other groups except the groups written in the first part from among the plurality of groups of the LDPC codeword, that is, the bits in the number of groups which correspond to the remainder when the number of groups constituting the LDPC codeword is divided by the number of columns, by the number of columns, and may write the divided bits in each column of the second part serially in a column direction.

For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R₁ number of rows. In addition, it is assumed that the LDPC codeword is formed of Y_(group) number of groups, the number of groups Y_(group) is not a multiple of C, and A×C+1=Y_(group) (A is an integer greater than 0). In other words, it is assumed that when the number of groups constituting the LDPC codeword is divided by the number of columns, the quotient is A and the remainder is 1.

In this case, as shown in FIGS. 9 and 10, the block interleaver 124 may divide each column into a first part including R₁ number of rows and a second part including R₂ number of rows. In this case, R₁ may correspond to the number of bits included in groups which can be written in each column in group units, and R₂ may be R₁ subtracted from the number of rows of each column.

That is, in the above-described example, the number of groups which can be written in each column in group units is A, and the first part of each column may be formed of as many rows as the number of bits included in A number of groups, that is, may be formed of as many rows as A×M number.

In this case, the block interleaver 124 writes the bits included in the groups which can be written in each column in group units, that is, A number of groups, in the first part of each column in the column direction.

That is, as shown in FIGS. 9 and 10, the block interleaver 124 writes the bits included in each of group Y₀, group Y₁, . . . , group Y_(n−1) in the 1^(st) to R₁ ^(th) rows of the first part of the 1^(st) column, writes bits included in each of group Y_(n), group Y_(n+1), . . . , group Y_(m−1) in the 1^(st) to R₁ ^(th) rows of the first part of the 2^(nd) column, . . . , writes bits included in each of group Y_(e), group Y_(e+1), . . . , group Y_(Ngroup-2) in the 1^(st) to R₁ ^(th) rows of the first part of the column C.

As described above, the block interleaver 124 writes the bits included in the groups which can be written in each column in group units in the first part of each column in in group units.

In other words, in the above exemplary embodiment, the bits included in each of group (Y0), group (Y1), . . . , group (Yn−1) may not be divided and all of the bits may be written in the first column, the bits included in each of group (Yn), group (Yn+1), . . . , group (Ym−1) may not be divided and all of the bits may be written in the second column, . . . , and the bits included in each of group (Ye), group (Ye+1), . . . , group (YNgroup-2) may not be divided and all of the bits may be written in the C column. As such, all groups interleaved by the first part are written in the same column of the first part.

Thereafter, the block interleaver 124 divides bits included in the other groups except the groups written in the first part of each column from among the plurality of groups, and writes the bits in the second part of each column in the column direction. In this case, the block interleaver 124 divides the bits included in the other groups except the groups written in the first part of each column by the number of columns, so that the same number of bits are written in the second part of each column, and writes the divided bits in the second part of each column in the column direction.

In the above-described example, since A×C+1=Y_(group), when the groups constituting the LDPC codeword are written in the first part serially, the last group Y_(Ngroup-1) of the LDPC codeword is not written in the first part and remains. Accordingly, the block interleaver 124 divides the bits included in the group Y_(Ngroup-1) by C as shown in FIG. 9, and writes the divided bits (that is, the bits corresponding to the quotient when the bits included in the last group (Y_(Ngroup-1)) are divided by C) in the second part of each column serially.

That is, the block interleaver 124 writes the bits in the 1^(st) to R₂ ^(th) rows of the second part of the 1^(st) column, writes the bits in the 1^(st) to R₂ ^(th) rows of the second part of the 2^(nd) column, . . . , etc., and writes the bits in the 1^(st) to R₂ ^(th) rows of the second part of the column C. In this case, the block interleaver 124 may write the bits in the second part of each column in the column direction as shown in FIG. 9.

That is, in the second part, the bits constituting the bit group may not be written in the same column and may be written in the plurality of columns. In other words, in the above example, the last group (Y_(Ngroup-1)) is formed of M bits and thus, the bits included in the last group (Y_(Ngroup-1)) may be divided by M/C and written in each column. Accordingly, in at least some groups which are interleaved by the second part, the bits included in at least some groups are divided and written in at least two columns constituting the second part.

In the above-described example, the block interleaver 124 writes the bits in the second part in the column direction. However, this is merely an example. That is, the block interleaver 124 may write the bits in the plurality of columns of the second parts in a row direction. In this case, the block interleaver 124 may write the bits in the first part in the same method as described above.

Specifically, referring to FIG. 10, the block interleaver 124 writes the bits from the 1^(st) row of the second part in the 1^(st) column to the 1^(st) row of the second part in the column C, writes the bits from the 2^(nd) row of the second part in the 1^(st) column to the 2^(nd) row of the second part in the column C, . . . , etc., and writes the bits from the R₂ ^(th) row of the second part in the 1^(st) column to the R₂ ^(th) row of the second part in the column C.

On the other hand, the block interleaver 124 reads the bits written in each row of each part serially in the row direction. That is, as shown in FIGS. 9 and 10, the block interleaver 124 reads the bits written in each row of the first part of the plurality of columns serially in the row direction, and reads the bits written in each row of the second part of the plurality of columns serially in the row direction.

Accordingly, the block interleaver 124 may interleave a part of a plurality of groups constituting the LDPC codeword in group units, and divide and interleave the remaining groups.

As described above, the block interleaver 124 may interleave the plurality of groups in the methods described above with reference to FIGS. 8 to 10.

In particular, in the case of FIG. 9, the bits included in the group which does not belong to the first part are written in the second part in the column direction and read in the row direction. In view of this, the order of the bits included in the group which does not belong to the first part is rearranged. Since the bits included in the group which does not belong to the first part are interleaved as described above, Bit Error Rate (BER)/Frame Error Rate (FER) performance can be improved in comparison with a case in which such bits are not interleaved.

However, the group which does not belong to the first part may not be interleaved as shown in FIG. 10. That is, since the block interleaver 124 writes and read the bits included in the group which does not belong to the first part on and from the second part in the row direction, the order of the bits included in the group which does not belong to the first part is not changed and the bits are output to the modulator 130 serially. In this case, the bits included in the group which does not belong to the first part may be output serially and mapped onto a modulation symbol.

In FIGS. 9 and 10, the last single group of the plurality of groups is written in the second part. However, this is merely an example. The number of groups written in the second part may vary according to the total number of groups of the LDPC codeword, the number of columns and rows, the number of transmission antennas, etc.

The block interleaver 124 may have a different configuration according to whether bits included in a same group are mapped onto a single bit of each modulation symbol or bits included in a same group are mapped onto two bits of each modulation symbol.

On the other hand, in the case of a transceiving system using a plurality of antennas, the number of columns constituting the block interleaver 124 may be determined by considering the number of bits constituting a modulation symbol and the number of used antennas simultaneously. For example, when bits included in a same group are mapped onto a single bit in a modulation symbol and two antennas are used, the block interleaver 124 may determine the number of columns to be two times the number of bits constituting the modulation symbol.

First, when bits included in the same group are mapped onto a single bit of each modulation symbol, the block interleaver 124 may have configurations as shown in Tables 16 and 17:

TABLE 16 N_(ldpc) = 64800 16 64 256 1024 4096 QPSK QAM QAM QAM QAM QAM C 2 4 6 8 10 12 R₁ 32400 16200 10800 7920 6480 5400 R₂ 0 0 0 180 0 0

TABLE 17 N_(ldpc) = 16200 16 64 256 1024 4096 QPSK QAM QAM QAM QAM QAM C 2 4 6 8 10 12 R₁ 7920 3960 2520 1800 1440 1080 R₂ 180 90 180 225 180 270

Herein, C (or N_(C)) is the number of columns of the block interleaver 124, R₁ is the number of rows constituting the first part in each column, and R₂ is the number of rows constituting the second part in each column.

Referring to Tables 16 and 17, the number of a plurality of columns has the same value as a modulation degree according to a modulation method, and each of a plurality of columns is formed of rows corresponding to the number of bits constituting the LDPC codeword divided by the number of a plurality of columns.

For example, when the length N_(ldpc) of the LDPC codeword is 64800 and the modulation method is 16-QAM, the block interleaver 124 is formed of 4 columns as the modulation degree is 4 in the case of 16-QAM, and each column is formed of rows as many as R₁+R₂=16200(=64800/4).

Meanwhile, referring to Tables 16 and 17, when the number of groups constituting an LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R₁ corresponds to the number of rows constituting each column, and R₂ is 0. In addition, when the number of groups constituting an LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the groups by dividing each column into the first part formed of R₁ number of rows, and the second part formed of R₂ number of rows.

When the number of columns of the block interleaver 124 is equal to the number of bits constituting a modulation symbol, bits included in a same group are mapped onto a single bit of each modulation symbol as shown in Tables 16 and 17.

For example, when N_(ldpc)=64800 and the modulation method is 16-QAM, the block interleaver 124 may use four (4) columns each including 16200 rows. In this case, a plurality of groups of an LDPC codeword are written in the four (4) columns in group units and bits written in the same row in each column are output serially. In this case, since four (4) bits constitute a single modulation symbol in the modulation method of 16-QAM, bits included in the same group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a group written in the 1^(st) column may be mapped onto the first bit of each modulation symbol.

On the other hand, when bits included in a same group are mapped onto two bits of each modulation symbol, the block interleaver 124 may have configurations as shown in Tables 18 and 19:

TABLE 18 N_(ldpc) = 64800 16 64 256 1024 4096 QPSK QAM QAM QAM QAM QAM C 1 2 3 4 5 6 R₁ 64800 32400 21600 16200 12960 10800 R₂ 0 0 0 0 0 0

TABLE 19 N_(ldpc) = 16200 16 64 256 1024 4096 QPSK QAM QAM QAM QAM QAM C 1 2 3 4 5 6 R₁ 16200 7920 5400 3960 3240 2520 R₂ 0 180 0 90 0 180

Herein, C (or N_(C)) is the number of columns of the block interleaver 124, R₁ is the number of rows constituting the first part in each column, and R₂ is the number of rows constituting the second part in each column.

Referring to Tables 18 and 19, when the number of groups constituting an LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R₁ corresponds to the number of rows constituting each column, and R₂ is 0. In addition, when the number of groups constituting an LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the groups by dividing each column into the first part formed of R₁ number of rows, and the second part formed of R₂ number of rows.

When the number of columns of the block interleaver 124 is half of the number of bits constituting a modulation symbol as shown in Tables 18 and 19, bits included in a same group are mapped onto two bits of each modulation symbol.

For example, when N_(ldpc)=64800 and the modulation method is 16-QAM, the block interleaver 124 may use two (2) columns each including 32400 rows. In this case, a plurality of groups of an LDPC codeword are written in the two (2) columns in group units and bits written in the same row in each column are output serially. Since four (4) bits constitute a single modulation symbol in the modulation method of 16-QAM, bits output from two rows constitute a single modulation symbol. Accordingly, bits included in the same group, that is, bits output from a single column, may be mapped onto two bits of each modulation symbol. For example, bits included in a group written in the 1^(st) column may be mapped onto bits existing in any two positions of each modulation symbol.

Referring to Tables 16 to 19, the total number of rows of the block interleaver 124, that is, R₁+R₂, is N_(ldpc)/C.

In addition, the number of rows of the first part, R₁, is an integer multiple of the number of bits included in each group, M (e.g., M=360), and maybe expressed as └N_(group)/C┘×M, and the number of rows of the second part, R₂, may be N_(ldpc)/C−R₁. Herein, └N_(group)/C┘ is the largest integer below N_(group)/C. Since R₁ is an integer multiple of the number of bits included in each group, M, bits may be written in R₁ in group units.

In addition, when the number of groups of an LDPC codeword is not a multiple of the number of columns, it can be seen from Tables 16 to 19 that the block interleaver 124 interleaves a plurality of groups of the LDPC codeword by dividing each column into two parts.

Specifically, the length of an LDPC codeword divided by the number of columns is the total number of rows included in the each column. In this case, when the number of groups of the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of groups of the LDPC codeword is not a multiple of the number of columns, each column is divided into two parts.

For example, it is assumed that the number of columns of the block interleaver 124 is identical to the number of bits constituting a modulation symbol, and an LDPC codeword is formed of 64800 bits as shown in Table 16. In this case, each group of the LDPC codeword is formed of 360 bits, and the LDPC codeword is formed of 64800/360(=180) groups.

When the modulation method is 16-QAM, the block interleaver 124 may use four (4) columns and each column may have 64800/4(=16200) rows.

In this case, since the number of groups of an LDPC codeword divided by the number of columns is 180/4(=45), bits can be written in each column in group units without dividing each column into two parts. That is, bits included in 45 groups which is the quotient when the number of groups constituting the LDPC codeword is divided by the number of columns, that is, 45×360(=16200) bits can be written in each column.

However, when the modulation method is 256-QAM, the block interleaver 124 may use eight (8) columns and each column may have 64800/8(=8100) rows.

In this case, since the number of groups of an LDPC codeword divided by the number of columns is 180/8=22.5, the number of groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight (8) columns into two parts to perform interleaving in group units.

In this case, since the bits should be written in the first part of each column in group units, the number of groups which can be written in the first part of each column in group units is 22 which is the quotient when the number of groups constituting the LDPC codeword is divided by the number of columns, and accordingly, the first part of each column has 22×360(=7920) rows. Accordingly, 7920 bits included in 22 groups may be written in the first part of each column.

The second part of each column has rows which are the rows of the first part subtracted from the total rows of each column. Accordingly, the second part of each column includes 8100−7920(=180) rows.

In this case, the bits included in the other group which has not been written in the first part are divided and written in the second part of each column.

Specifically, since 22×8(=176) groups are written in the first part, the number of groups to be written in the second part is 180−176 (=4) (for example, group Y₁₇₆, group Y₁₇₇, group Y₁₇₈, and group Y₁₇₉ from among group Y₀, group Y₁, group Y₂, . . . , group Y₁₇₈, and group Y₁₇₉ constituting an LDPC codeword).

Accordingly, the block interleaver 124 may write the four (4) groups which have not been written in the first part and remains from among the groups constituting the LDPC codeword in the second part of each column serially.

That is, the block interleaver 124 may write 180 bits of the 360 bits included in the group Y₁₇₆ in the 1^(st) row to the 180^(th) row of the second part of the 1^(st) column in the column direction, and may write the other 180 bits in the 1^(st) row to the 180^(th) row of the second part of the 2^(nd) column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the group Y₁₇₇ in the 1^(st) row to the 180^(th) row of the second part of the 3^(rd) column in the column direction, and may write the other 180 bits in the 1^(st) row to the 180^(th) row of the second part of the 4^(th) column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the group Y₁₇₈ in the 1^(st) row to the 180^(th) row of the second part of the 5^(th) column in the column direction, and may write the other 180 bits in the 1^(st) row to the 180^(th) row of the second part of the 6^(th) column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the group Y₁₇₉ in the 1^(st) row to the 180^(th) row of the second part of the 7^(th) column in the column direction, and may write the other 180 bits in the 1^(st) row to the 180^(th) row of the second part of the 8^(th) column in the column direction.

Accordingly, the bits included in the group which has not been written in the first part and remains are not written in the same column in the second part and may be divided and written in the plurality of columns.

Hereinafter, the block interleaver of FIG. 4 according to an exemplary embodiment will be explained in detail with reference to FIG. 11.

In a group-interleaved LDPC codeword (v₀, v₁, . . . , v_(N) _(ldpc) ⁻¹), Y_(j) is continuously arranged like V={Y₀, Y₁, . . . Y_(N) _(group) ⁻¹}.

The LDPC codeword after group interleaving may be interleaved by the block interleaver 124 as shown in FIG. 11. In this case, the block interleaver 124 divide a plurality of columns into the first part (Part 1) and the second part (Part 2) based on the number of columns of the block interleaver 124 and the number of bits of groups. In this case, in the first part, the bits constituting groups may be written in the same column, and in the second part, the bits constituting groups may be written in a plurality of columns.

In the block interleaver 124, the data bits vi from the group-wise interleaver 122 are written serially into the block interleaver column-wise starting in the first part and continuing column-wise finishing in the second part, and then read out serially row-wise from the first part and then row-wise from the second part. Accordingly, the bits included in the same group in the first part may be mapped onto single bit of each modulation symbol.

In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 vary according to a modulation method as in Table 20 presented below. The first part and the second part block interleaving configurations for each modulation format and code length are specified in Table 20. Herein, the number of columns of the block interleaver 124 may be equal to the number of bits constituting a modulation symbol. In addition, a sum of the number of rows of the first part, N_(r1) and the number of rows of the second part, N_(r2), is equal to N_(ldpc)/N_(C) (herein, N_(C) is the number of columns). In addition, since N_(r1)(=└Ngroup/Nc┘×360) is a multiple of 360, so that multiple of bit groups are written into the first part of block interleaver.

TABLE 20 Rows in Part 1 N_(r1) Rows in Part 2 N_(r2) N_(ldpc) = N_(ldpc) = N_(ldpc) = N_(ldpc) = Columns Modulation 64800 16200 64800 16200 N_(c) QPSK 32400 7920 0 180 2  16-QAM 16200 3960 0 90 4  64-QAM 10800 2520 0 180 6  256-QAM 7920 1800 180 225 8 1024-QAM 6480 1440 0 180 10 4096-QAM 5400 1080 0 270 12

Hereinafter, an operation of the block interleaver 124 will be explained in detail.

Specifically, as shown in FIG. 11, the input bit v_(i) (0≦i<N_(C)×N_(r1)) is written in r_(i) row of c_(i) column of the first part of the block interleaver 124. Herein, c_(i) and r_(i) are

$c_{i} = \left\lfloor \frac{i}{N_{r\; 1}} \right\rfloor$

and r_(i)=(i mod N_(r1)), respectively.

In addition, the input bit v_(i) (N_(C)×N_(r1)≦i<N_(ldpc)) is written in an r_(i) row of c_(i) column of the second part of the block interleaver 124. Herein, c_(i) and r_(i) are

$c_{i} = \left\lfloor \frac{\left( {i - {N_{C} \times N_{r\; 1}}} \right)}{N_{r\; 2}} \right\rfloor$

and r_(i)=N_(r1)+{(i−N_(C)×N_(r1))mod N_(r2)}, respectively.

An output bit q_(j) (0≦j<N_(ldpc)) is read from c_(j) column of r_(j) row. Herein, r_(j) and c_(j) are

$r_{j} = \left\lfloor \frac{j}{N_{c}} \right\rfloor$

and c_(j)=(j mod N_(C)), respectively.

For example, when the length N_(ldpc) of an LDPC codeword is 64800 and the modulation method is 256-QAM, an order of bits output from the block interleaver 124 may be (q₀,q₁,q₂, . . . , q₆₃₃₅₇,q₆₃₃₅₈,q₆₃₃₅₉,q₆₃₃₆₀,q₆₃₃₆₁, . . . , q₆₄₇₉₉)=(v₀,v₇₉₂₀,v₁₅₈₄₀, . . . , v₄₇₅₁₉,v₅₅₄₃₉,v₆₃₃₅₉,v₆₃₃₆₀,v₆₃₅₄₀, . . . , v₆₄₇₉₉). Herein, the indexes of the right side of the foregoing equation may be specifically expressed for the eight (8) columns as 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, . . . , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, . . . , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

Meanwhile, in the above example, the number of columns constituting the block interleaver 124 may be the same value as a modulation degree or half the modulation degree, but this is only an example. The number of columns constituting the block interleaver 124 may be a multiple value of the modulation degree. In this case, the number of rows constituting each column may be the length of the LDPC codeword divided by the number of columns.

For example, in case that the modulation method is QPSK (that is, the modulation degree is 2), the number of columns may be 4 instead of 2. In this case, if the length N_(ldpc) of the LDPC codeword is 16200, the number of rows constituting each column may be 4050(=16200/4).

Meanwhile, even when the number of columns is the multiple value of the modulation degree, the block interleaver 124 may perform interleaving using the same method as when the number of columns is the same value as the modulation degree of half the modulation degree, so detailed description thereof will not be provided.

In this case, the number of columns constituting the block interleaver 124 may have the same value as the modulation degree or the integer multiple of the modulation degree and thus, the number of the second part may be the same value as a quotient when the number of bits included in all bit groups excluding groups corresponding to the first part is divided by the modulation degree or the multiple of the modulation degree.

Referring back to FIG. 1, the modulator 130 modulates an interleaved LDPC codeword according to a modulation method to generate a modulation symbol. Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword and modulate the demultiplexed LDPC codeword and map it onto a constellation, thereby generating a modulation symbol.

In this case, the modulator 130 may generate a modulation symbol using bits included in each of a plurality of groups.

In other words, as described above, the bits included in different groups are written in each column of the block interleaver 124, and the block interleaver 124 reads the bits written in each column in a row direction. In this case, the modulator 130 generates a modulation symbol by mapping the bits read in each column onto each bit of the modulation symbol. Accordingly, each bit of the modulation symbol belongs to a different group.

For example, it is assumed that the modulation symbol consists of C bits (C refers to the number of bits). In this case, the bits which are read from each row of C columns of the block interleaver 124 may be mapped onto each bit of the modulation symbol and thus, each bit of the modulation symbol consisting of C bits belong to C different groups.

Hereinbelow, the above feature will be described in greater detail.

First, the modulator 130 demultiplexes the interleaved LDPC codeword. To achieve this, the modulator 130 may include a demultiplexer (not shown) to demultiplex the interleaved LDPC codeword.

The demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, the demultiplexer (not shown) performs serial-to-parallel conversion with respect to the interleaved LDPC codeword, and demultiplexes the interleaved LDPC codeword into a cell having a predetermined number of bits (or a data cell).

For example, as shown in FIG. 12, the demultiplexer (not shown) receives the LDPC codeword Q=(q₀, q₁, q₂, . . . ) output from the interleaver 120, outputs the received LDPC codeword bits to one of a plurality of substreams serially, converts the input LDPC codeword bits into cells, and outputs the cells.

Herein, the number of substreams, N_(substreams), may be equal to the number of bits constituting a modulation symbol, η_(mod), and the number of bits constituting the cell may be equal to N_(ldpc)/η_(mod). η_(mod) varying according to a modulation method and the number of cells generated according to the length N_(ldpc) of the LDPC codeword are as in Table 21 presented below:

TABLE 21 Number of output Number of output Modulation data cells for data cells for mode η_(MOD) N_(ldpc) = 64 800 N_(ldpc) = 16 200 QPSK 2 32 400 8 100 16-QAM 4 16 200 4 050 64-QAM 6 10 800 2 700 256-QAM  8  8 100 2 025 1024-QAM  10  6 480 1 620

Bits having the same index in each of the plurality of sub-streams may constitute a same cell. That is, in FIG. 12, each cell may be expressed as (y_(0,0), y_(1,0), . . . y_(ηMOD−1,0)), (y_(0,1), y_(1,1), . . . , y_(ηMOD−1,1)).

The demultiplexer (not shown) may demultiplex input LDPC codeword bits in various methods. That is, the demultiplexer (not shown) may change an order of the LDPC codeword bits and output the bits to each of the plurality of substreams, or may output the bits to each of the plurality of streams serially without changing the order of the LDPC codeword bits. These operations may be determined according to the number of columns used for interleaving in the block interleaver 124.

Specifically, when the block interleaver 124 includes as many columns as half of the number of bits constituting a modulation symbol, the demultiplexer (not shown) may change the order of the input LDPC codeword bits and output the bits to each of the plurality of sub-streams. An example of a method for changing the order is illustrated in Table 22 presented below:

TABLE 22 Modulation format QPSK Input bit 0 1 di mod Nsubstreams output bit-number

0 1 Modulation format 16 QAM Input bit 0 1 2 3 di mod Nsubstreams output bit-number

0 2 1 3 Modulation format 64 QAM Input bit 0 1 2 3 4 5 di mod Nsubstreams output bit-number

0 3 1 4 2 5 Modulation format 256 QAM Input bit 0 1 2 3 4 5 6 7 di mod Nsubstreams output bit-number

0 4 1 5 2 6 3 7 Modulation format 1024 QAM Input bit 0 1 2 3 4 5 6 7 8 9 di mod Nsubstreams output bit-number

0 5 1 6 2 7 3 8 4 9 Modulation format 4096 QAM Input bit 0 1 2 3 4 5 6 7 8 9 10 11 di mod Nsubstreams output bit-number

0 6 1 7 2 8 3 9 4 10 5 11

indicates data missing or illegible when filed

According to Table 22, when the modulation method is 16-QAM for example, the number of substreams is four (4) since the number of bits constituting the modulation symbol is four (4) in the case of 16-QAM. In this case, the demultiplexer (not shown) may output, from among the serially input bits, bits with an index i satisfying i mod 4=0 to the 0^(th) substream, bits with an index i satisfying i mod 4=1 to the 2^(nd) substream, bits with an index i satisfying i mode 4=2 to the 1^(st) substream, and bits with an index i satisfying i mode 4=3 to the 3^(rd) substream.

Accordingly, the LDPC codeword bits input to the demultiplexer (not shown), (q₀, q₁, q₂ . . . . ), may be output as cells like (y_(0,0), y_(1,0), y_(2,0), y_(3,0))=(q₀, q₂, q₁, q₃), (y_(0,1), y_(1,1), y_(2,1), y_(3,1))=(q₄, q₆, q₅, q₇), . . . .

When the block interleaver 124 includes the same number of columns as the number of bits constituting a modulation symbol, the demultiplexer (not shown) may output the input LDPC codeword bits to each of the plurality of streams serially without changing the order of the bits. That is, as shown in FIG. 13, the demultiplexer (not shown) may output the input LDPC codeword bits (q₀, q₁, q₂, . . . ) to each of the substreams serially, and accordingly, each cell may be configured as (y_(0,0),y_(1,0), . . . , y_(MOD−1,0))=(q₀,q₁, . . . , q_(ηMOD−1)), (y_(0,1),y_(1,1), . . . , y_(ηMOD−1,1))=(q_(ηMOD),q_(ηMOD+1), . . . , q_(2×ηMOD−1)) . . . .

In the above-described example, the demultiplexer (not shown) outputs the input LDPC codeword bits to each of the plurality of streams serially without changing the order of the bits. However, this is merely an example. That is, according to an exemplary embodiment, when the block interleaver 124 includes the same number of columns as the number of bits constituting a modulation symbol, the demultiplexer (not shown) may be omitted.

The modulator 130 may map the demultiplexed LDPC codeword onto modulation symbols. However, when the demultiplexer (not shown) is omitted as described above, the modulator 130 may map LDPC codeword bits output from the interleaver 120, that is, block-interleaved LDPC codeword bits, onto modulation symbols.

The modulator 130 may modulate bits (that is, cells) output from the demultiplexer (not shown) in various modulation methods such as QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, etc. When the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM and 4096-QAM, the number of bits constituting a modulation symbol, η_(MOD) (that is, a modulation degree), may be 2, 4, 6, 8, 10 and 12, respectively.

In this case, since each cell output from the demultiplexer (not shown) is formed of as many bits as the number of bits constituting a modulation symbol, the modulator 130 may generate a modulation symbol by mapping each cell output from the demultiplexer (not shown) onto a constellation point serially. Herein, a modulation symbol corresponds to a constellation point on the constellation.

However, when the demultiplexer (not shown) is omitted, the modulator 130 may generate modulation symbols by grouping a predetermined number of bits from interleaved bits serially and mapping the predetermined number of bits onto constellation points. In this case, the modulator 130 may generate the modulation symbols by using η_(MOD) number of bits serially according to a modulation method.

The modulator 130 may modulate by mapping cells output from the demultiplexer (not shown) onto constellation points in a uniform constellation (UC) method.

The uniform constellation method refers to a method for mapping a modulation symbol onto a constellation point so that a real number component Re(z_(q)) and an imaginary number component Im(z_(q)) of a constellation point have symmetry and the modulation symbol is placed at equal intervals. Accordingly, at least two of modulation symbols mapped onto constellation points in the uniform constellation method may have the same demodulation performance.

Examples of the method for generating a modulation symbol in the uniform constellation method according to an exemplary embodiment are illustrated in Tables 23 to 30 presented below, and an example of a case of a uniform constellation 64-QAM is illustrated in FIG. 14.

TABLE 23 y_(0, q) 1 0 Re(z_(q)) −1 1

TABLE 24 Y_(1, q) 1 0 Im(z_(q)) −1 1

TABLE 25 y_(0, q) 1 1 0 0 y_(2, q) 0 1 1 0 Re(z_(q)) −3 −1 1 3

TABLE 26 y_(1, q) 1 1 0 0 y_(3, q) 0 1 1 0 Im(z_(q)) −3 −1 1 3

TABLE 27 y_(0.q) 1 1 1 1 0 0 0 0 y_(2.q) 0 0 1 1 1 1 0 0 y_(4.q) 0 1 1 0 0 1 1 0 Re(z_(q)) −7 −5 −3 −1 1 3 5 7

TABLE 28 y_(1.q) 1 1 1 1 0 0 0 0 y_(3.q) 0 0 1 1 1 1 0 0 y_(5.q) 0 1 1 0 0 1 1 0 Im(z_(q)) −7 −5 −3 −1 1 3 5 7

TABLE 29 y_(0.q) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 y_(2.q) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 y_(4.q) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 y_(6.q) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Re(z_(q)) −15 −13 −11 −9 −7 −5 −3 −1 1 3 5 7 9 11 13 15

TABLE 30 y_(1.q) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 y_(3.q) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 y_(5.q) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 y_(7.q) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Im(z_(q)) −15 −13 −11 −9 −7 −5 −3 −1 1 3 5 7 9 11 13 15

Tables 23 and 24 are used for determining a real number component Re(z_(q)) and an imaginary number component Im(z_(q)) when the modulation is performed in a QPSK method, Tables 25 and 26 are used for determining a real number component Re(z_(q)) and an imaginary number component Im(z_(q)) when the modulation is performed in a 16-QAM method, Tables 27 and 28 are used for determining a real number component Re(z_(q)) and an imaginary number component Im(z_(q)) when the modulation is performed in a 64-QAM method, and Tables 29 and 30 are used for determining a real number component Re(z_(q)) and an imaginary number component Im(z_(q)) when the modulation is performed in a 256-QAM method.

Referring to Tables 23 to 30, performance (e.g., reliability) varies according to whether a plurality of bits constituting a modulation symbol correspond to most significant bits (MSBs) or least significant bits (LSBs).

For example, in the case of 16-QAM, from among four (4) bits constituting a modulation symbol, each of the first and second bits determines a sign of each of the real number component Re(z_(q)) and the imaginary number component Im(z_(q)) of a constellation point onto which a modulation symbol is mapped, and the third and fourth bits determine a size of the constellation point onto which the modulation symbol is mapped.

In this case, the first and second bits for determining the sign from among the four (4) bits constituting the modulation symbol have a higher reliability than the third and fourth bits for determining the size.

In another example, in the case of 64-QAM, from among six (6) bits constituting a modulation symbol, each of the first and second bits determines a sign of each of the real number component Re(z_(q)) and the imaginary number component Im(z_(q)) of a constellation point onto which the modulation symbol is mapped. In addition, the third to sixth bits determine a size of the constellation point onto which the modulation symbol is mapped. From among these bits, the third and fourth bits determine a relatively large size, and the fifth and sixth bits determine a relatively small size (for example, the third bit determines which of sizes (−7, −5) and (−3, −1) corresponds to the constellation point onto which the modulation symbol is mapped, and, when (−7, −5) is determined by the third bit, the fourth bit determines which of −7 and −5 corresponds to the size of the constellation point.).

In this case, the first and second bits for determining the sign from among the six bits constituting the modulation symbol have the highest reliability, and the third and fourth bits for determining the relatively large size has the higher reliability than the fifth and sixth bits for determining the relatively small size.

As described above, in the case of the uniform constellation method, the bits constituting a modulation symbol have different reliability according to mapping locations in the modulation symbol.

The modulator 130 may modulate by mapping cells output from the demultiplexer (not shown) onto constellation points in a non-uniform constellation (NUC) method.

Specifically, the modulator 130 may modulate bits output from the demultiplexer (not shown) in various modulation methods such as non-uniform QPSK, non-uniform 16-QAM, non-uniform 64-QAM, non-uniform 256-QAM, non-uniform 1024-QAM, non-uniform 4096-QAM, etc.

Hereinafter, a method for generating a modulation symbol by using the non-uniform constellation method according to an exemplary embodiment will be explained.

First, the non-uniform constellation method has the following characteristics:

In the non-uniform constellation method, the constellation points may not regularly be arranged unlike in the uniform constellation method. Accordingly, when the non-uniform constellation method is used, performance for a signal-to-noise ratio (SNR) less than a specific value can be improved and a high SNR gain can be obtained in comparison to the uniform constellation method.

In addition, the characteristics of the constellation may be determined by one or more parameters such as a distance between constellation points. Since the constellation points are regularly distributed in the uniform constellation, the number of parameters for specifying the uniform constellation method may be one (1). However, the number of parameters necessary for specifying the non-uniform constellation method is relatively larger and the number of parameters increases as the constellation (e.g., the number of constellation points) increases.

In the case of the non-uniform constellation method, an x-axis and a y-axis may be designed to be symmetric to each other or may be designed to be asymmetric to each other. When the x-axis and the y-axis are designed to be asymmetric to each other, improved performance can be guaranteed, but decoding complexity may increase.

Hereinafter, an example of a case in which the x-axis and the y-axis are designed to be asymmetric to each other will be explained. In this case, once a constellation point of the first quadrant is defined, locations of constellation points in the other three quadrants may be determined as follows. For example, when a set of constellation points defined for the first quadrant is X, the set becomes −conj(X) in the case of the second quadrant, becomes conj(X) in the case of the third quadrant, and becomes −(X) in the case of the fourth quadrant.

That is, once the first quadrant is defined, the other quadrants may be expressed as follows:

-   -   1 Quarter (first quadrant)=X     -   2 Quarter (second quadrant)=−conj(X)     -   3 Quarter (third quadrant)=conj(X)     -   4 Quarter (fourth quadrant)=−X

Specifically, when the non-uniform M-QAM is used, M number of constellation points may be defined as z={z₀, z₁, . . . , z_(M−1)}. In this case, when the constellation points existing in the first quadrant are defined as {x₀, x₁, x₂, . . . , x_(M/4−1)}, z may be defined as follows:

-   -   from z₀ to Z_(M/4−1)=from x₀ to x_(M/4)     -   from Z_(M/4) to Z_(2×M/4−1)=−conj(from x₀ to x_(M/4))     -   from Z_(2×M/4) to Z_(3×M/4−1)=conj(from x₀ to x_(M/4))     -   from Z_(3×M/4) to Z_(4×M/4−1)=−(from x₀ to x_(M/4))

Accordingly, the modulator 130 may map the bits [y₀, . . . , y_(m−1)] output from the demultiplexer (not shown) onto constellation points in the non-uniform constellation method by mapping the output bits onto z_(L) having an index of

$L = {\sum\limits_{i = 0}^{m - 1}{\left( {y_{1} \times 2^{m - 1}} \right).}}$

An example of the constellation of the non-uniform constellation method is illustrated in FIGS. 15 to 19.

An example of the method for modulating asymmetrically in the non-uniform constellation method in the modulator 130 is illustrated as in Tables 31 to 34 presented below. That is, according to an exemplary embodiment, modulation is performed in the non-uniform constellation method by defining constellation points existing in the first quadrant and defining constellations points existing in the other quadrants based on Tables 31 to 34.

TABLE 31 Input data cell y Constellation point z_(s) (00) (1 + 1i)/{square root over (2)} (01) (1 − 1i)/{square root over (2)} (10) (−1 + 1i)/{square root over (2)} (11) (−1 − 1i)/{square root over (2)}

TABLE 32 x/Shape R6/15 R7/15 R8/15 R9/15 R10/15 x0 0.4530 + 0.2663i 1.2103 + 0.5026i 0.4819 + 0.2575i 0.4909 + 1.2007i 0.2173 + 0.4189i x1 0.2663 + 0.4530i 0.5014 + 1.2103i 0.2575 + 0.4819i 1.2007 + 0.4909i 0.6578 + 0.2571i x2 1.2092 + 0.5115i 0.4634 + 0.2624i 1.2068 + 0.4951i 0.2476 + 0.5065i 0.4326 + 1.1445i x3 0.5115 + 1.2092i 0.2624 + 0.4627i 0.4951 + 1.2068i 0.5053 + 0.2476i 1.2088 + 0.5659i x/Shape R11/15 R12/15 R13/15 x0 0.9583 + 0.9547i 0.2999 + 0.2999i 0.9517 + 0.9511i x1 0.9547 + 0.2909i 0.9540 + 0.2999i 0.9524 + 0.3061i x2 0.2921 + 0.9583i 0.2999 + 0.9540i 0.3067 + 0.9524i x3 0.2909 + 0.2927i 0.9540 + 0.9540i 0.3061 + 0.3067i

TABLE 33 x/Shape R64_6/15 R64_7/15 R64_8/15 R64_9/15 R64_10/15 x0 0.4387 + 1.6023i 0.3352 + 0.6028i 1.4827 + 0.2920i 0.3547 + 0.6149i 1.4388 + 0.2878i x1 1.6023 + 0.4387i 0.2077 + 0.6584i 1.2563 + 0.8411i 0.1581 + 0.6842i 1.2150 + 0.8824i x2 0.8753 + 1.0881i 0.1711 + 0.3028i 1.0211 + 0.2174i 0.1567 + 0.2749i 1.0386 + 0.2219i x3 1.0881 + 0.8753i 0.1556 + 0.8035i 0.8798 + 0.5702i 0.1336 + 0.2700i 0.8494 + 0.6145i x4 0.2202 + 0.9238i 0.6028 + 0.3345i 0.2920 + 1.4827i 0.6177 + 0.4030i 0.2931 + 1.4656i x5 0.2019 + 0.7818i 0.6577 + 0.2084i 0.8410 + 1.2563i 0.7262 + 0.1756i 0.8230 + 1.2278i x6 0.3049 + 0.8454i 0.3021 + 0.1711i 0.2174 + 1.0211i 0.3568 + 0.1756i 0.2069 + 1.0649i x7 0.2653 + 0.7540i 0.3028 + 0.1556i 0.5702 + 0.8798i 0.3771 + 0.1336i 0.5677 + 0.8971i x8 0.7818 + 0.2019i 0.5556 + 0.8922i 0.3040 + 0.1475i 0.5639 + 0.8864i 0.4119 + 0.1177i x9 0.9238 + 0.2202i 0.2352 + 1.0190i 0.3028 + 0.1691i 0.1980 + 1.0277i 0.3998 + 0.2516i x10 0.7540 + 0.2653i 0.8450 + 1.2619i 0.6855 + 0.1871i 0.8199 + 1.2515i 0.7442 + 0.1559i x11 0.8454 + 0.3049i 0.2922 + 1.4894i 0.6126 + 0.3563i 0.2854 + 1.4691i 0.5954 + 0.4328i x12 0.2675 + 0.2479i 0.8929 + 0.5549i 0.1475 + 0.3040i 0.8654 + 0.6058i 0.1166 + 0.1678i x13 0.2479 + 0.2675i 1.0197 + 0.2359i 0.1691 + 0.3028i 1.0382 + 0.2142i 0.1582 + 0.3325i x14 0.2890 + 0.2701i 1.2626 + 0.8457i 0.1871 + 0.6855i 1.2362 + 0.8416i 0.1355 + 0.7408i x15 0.2701 + 0.2890i 1.4894 + 0.2922i 0.3563 + 0.6126i 1.4663 + 0.2973i 0.3227 + 0.6200i x/Shape R64_11/15 R64_12/15 R64_13/15 x0 0.3317 + 0.6970i 1.0854 + 0.5394i 0.4108 + 0.7473i x1 0.1386 + 0.8824i 0.7353 + 0.4623i 0.1343 + 0.5338i x2 0.1323 + 0.4437i 1.0474 + 0.1695i 0.1570 + 0.9240i x3 0.1015 + 0.1372i 0.7243 + 0.1504i 0.1230 + 0.1605i x4 0.5682 + 0.4500i 1.0693 + 0.9408i 0.6285 + 0.4617i x5 0.6739 + 0.1435i 0.7092 + 0.8073i 0.3648 + 0.3966i x6 0.3597 + 0.3401i 1.4261 + 0.2216i 0.6907 + 0.1541i x7 0.3660 + 0.1204i 0.6106 + 1.1783i 0.3994 + 0.1308i x8 0.6004 + 0.8922i 0.1392 + 0.4078i 0.7268 + 0.8208i x9 0.2120 + 1.2253i 0.4262 + 0.4205i 1.0463 + 0.9495i x10 0.9594 + 1.0714i 0.1407 + 0.1336i 0.1866 + 1.2733i x11 0.5829 + 1.3995i 0.4265 + 0.1388i 0.5507 + 1.1793i x12 0.8439 + 0.5675i 0.1388 + 0.7057i 0.9283 + 0.5140i x13 0.9769 + 0.1959i 0.4197 + 0.7206i 1.2648 + 0.5826i x14 1.2239 + 0.6760i 0.1682 + 1.0316i 0.9976 + 0.1718i x15 1.3653 + 0.2323i 0.2287 + 1.3914i 1.3412 + 0.1944i

TABLE 34

indicates data missing or illegible when filed

Table 31 indicates non-uniform QPSK, table 32 indicates non-uniform 16-QAM, Table 42 indicates non-uniform 64-QAM, and table 33 indicates non-uniform 256-QAM, and different mapping methods may be applied according to a code rate.

On the other hand, when the non-uniform constellation is designed to have the x-axis and the y-axis symmetric to each other, constellation points may be expressed similarly to those of uniform QAM and an example is illustrated as in Tables 35 to 37 presented below:

TABLE 35 y_(0, q) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 y_(2. q) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 y_(4, q) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 y_(6, q) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 y_(8, q) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Re(z_(q)) −x₁₅ −x₁₄ −x₁₃ −x₁₂ −x₁₁ −x₁₀ −x₉ −x₈ −x₇ −x₆ −x₅ −x₄ −x₃ −x₂ −x₁ −1  y_(0, q) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 y_(2. q) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 y_(4, q) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 y_(6, q) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 y_(8, q) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Re(z_(q)) 1  x₁  x₂  x₃  x₄  x₅  x₆  x₇  x₈  x₉  x₁₀  x₁₁  x₁₂  x₁₃  x₁₄ x₁₅

TABLE 36 y_(1, q) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 y_(3. q) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 y_(5, q) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 y_(7, q) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 y_(9, q) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Im(z_(q)) −x₁₅ −x₁₄ −x₁₃ −x₁₂ −x₁₁ −x₁₀ −x₉ −x₈ −x₇ −x₆ −x₅ −x₄ −x₃ −x₂ −x₁ −1  y_(1, q) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 y_(3. q) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 y_(5, q) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 y_(7, q) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 y_(9, q) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Im(z_(q)) 1  x₁  x₂  x₃  x₄  x₅  x₆  x₇  x₈  x₉  x₁₀  x₁₁  x₁₂  x₁₃  x₁₄ x₁₅

TABLE 37 X/Shape R6/15 R7/15 R8/15 R9/15 R10/15 R11/15 R12/15 R13/15 x1 1.0003 1 1.0005 1 1.0772 1.16666667 2.5983 2.85714286 x2 1.0149 1.04 2.0897 2.78571429 2.8011 3.08333333 4.5193 4.85714286 x3 1.0158 1.04 2.0888 2.78571429 2.9634 3.33333333 6.1649 6.85714286 x4 2.6848 3 3.995 4.85714286 4.8127 5.16666667 8.2107 8.85714286 x5 2.6903 3.04 3.9931 4.85714286 5.1864 5.75 9.9594 11 x6 2.882 3.28 5.3843 6.85714286 6.7838 7.41666667 12.0321 13.2857143 x7 2.8747 3.32 5.3894 6.85714286 7.5029 8.5 13.9574 15.7142857 x8 4.7815 5.24 7.5206 9.14285714 9.238 10.0833333 16.2598 18.1428571 x9 4.7619 5.32 7.6013 9.28571429 10.32 11.5833333 18.4269 20.7142857 x10 5.5779 6.04 9.3371 11.5714286 12.0115 13.3333333 20.9273 23.4285714 x11 5.6434 6.28 9.8429 12.2142857 13.5356 15.25 23.4863 26.2857143 x12 7.3854 8.24 11.9255 14.6428571 15.6099 17.3333333 26.4823 29.2857143 x13 7.8797 8.84 13.3962 16.4285714 17.7524 19.75 29.7085 32.4285714 x14 9.635 11.04 15.8981 19.4285714 20.5256 22.4166667 33.6247 35.7142857 x15 11.7874 13.68 19.1591 23.2857143 24.1254 25.5833333 38.5854 39.4285714

Tables 35 and 37 are tables for determining the real number component Re(z_(q)) and the imaginary number component Im(z_(q)) when modulation is performed in the non-uniform 1024-QAM method. That is, Table 35 indicates the real number part of the 1024-QAM, and Table 36 indicates the imaginary number part of the 1024-QAM. In addition, Table 37 illustrate an example of a case in which modulation is performed in the non-uniform 1024-QAM method, and show x_(i) values of Tables 35 and 36.

Since the non-uniform constellation method asymmetrically map the modulation symbol onto the constellation point as shown in Tables 35 to 37, modulation symbols mapped onto constellation points may have different decoding performance. That is, bits constituting a modulation symbol may have different performance.

For example, referring to FIG. 15 illustrating an example of a case in which modulation is performed in the non-uniform 64-QAM method, a modulation symbol 10 may be configured as (y₀, y₁, y₂, y₃, y₄, y₅)=(0, 0, 1, 0, 1, 0), and performance (e.g., capacity) of bits constituting the modulation symbol 10 may have a relationship of C(y₀)>C(y₁)>C(y₂>C(y₃)>C(y₄)>C(y₅).

In addition, it is obvious that the constellation in the uniform constellation method and the non-uniform constellation method may be rotated and/or scaled (herein, the same or different scaling factor may be applied to a real number axis and an imaginary number axis), and other variations can be applied. In addition, the illustrated constellation indicates relevant locations of the constellation points and another constellation can be derived by rotation, scaling and/or other appropriate conversion.

As described above, the modulator 130 may map modulation symbols onto constellation points by using uniform constellation methods and non-uniform constellation methods. In this case, bits constituting a modulation symbol may have different performance as described above.

LDPC codeword bits may have different codeword characteristics according to a configuration of a parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1 existing in the columns of the parity check matrix, that is, a column degree.

Accordingly, the interleaver 120 may interleave to map the LDPC codeword bits onto modulation symbols by considering both the codeword characteristic of the LDPC codeword bits and the reliability of the bits constituting a modulation symbol.

In particular, since bits constituting a modulation symbol have different performance when a non-uniform QAM is used, the block interleaver 124 configures the number of columns to be identical to the number of bits constituting a modulation symbol such that one of a plurality of groups of an LDPC codeword can be mapped onto bits each of which exists on a same location of each modulation symbol.

That is, when LDPC codeword bits of high decoding performance are mapped onto high reliability bits from among bits of each modulation symbol, a receiver side may show high decoding performance, but there is a problem that the LDPC codeword bits of the high decoding performance are not received. In addition, when the LDPC codeword bits of high decoding performance are mapped onto low reliability bits from among the bits of the modulation symbol, initial reception performance is excellent, and thus, overall performance is also excellent. However, when many bits showing poor decoding performance are received, error propagation may occur.

Accordingly, when LDPC codeword bits are mapped onto modulation symbols, an LDPC codeword bit having a specific codeword characteristic is mapped onto a specific bit of a modulation symbol by considering both codeword characteristics of the LDPC codeword bits and reliability of the bits of the modulation symbol, and is transmitted to a receiver side. Accordingly, the receiver side can achieve both the high reception performance and the high decoding performance.

In this case, since the LDPC codeword is divided into groups each formed of M (=360) number of bits having the same codeword characteristic and the bits are mapped respectively onto a bit of a specific location of each modulation symbol in group units, bits having a specific codeword characteristic can be mapped onto the specific location of each modulation symbol more effectively. In addition, the number of bits constituting the group may be an aliquot part of M as described above. However, the number of codeword bits constituting the group is limited to M for convenience of explanation.

That is, the modulator 130 can map at least one bit included in a predetermined group from among the plurality of groups constituting the LDPC codeword onto a predetermined bit of each modulation symbol. Herein, each of the plurality of groups may be formed of M (=360) number of bits.

For example, in the case of 16-QAM, at least one bit included in a predetermined group from among the plurality of groups may be mapped onto a first bit of each modulation symbol, or may be mapped onto a first bit and a second bit.

The modulator 130 can map at least one bit included in a predetermined group from among the plurality of groups onto a predetermined bit of each modulation symbol for the following reasons.

As described above, the block interleaver 124 interleaves a plurality of groups of an LDPC codeword in group units, the demultiplexer (not shown) demultiplexes bits output from the block interleaver 124, and the modulator 130 maps demultiplexed bits (that is, cells) onto modulation symbols serially.

Accordingly, the group interleaver 122, which is placed before the block interleaver 124, interleaves the LDPC codeword in group units such that groups including bits to be mapped onto bits of specific locations of a modulation symbol can be written in the same column of the block interleaver 124, considering a demultiplexing operation of the demultiplexer (not shown).

Specifically, the group interleaver 122 may rearrange the order of a plurality of groups of an LDPC codeword in group units such that at least one group including bits to be mapped onto the same location of different modulation symbols are serially arranged adjacent to one another, thereby allowing the block interleaver 122 to write a predetermined group on a predetermined column. That is, the group interleaver 122 interleaves the plurality of groups of the LDPC codeword in group units based on the above-described Tables 12 to 15, so that at least one group including bits to be mapped onto the same location of each modulation symbol are arranged to be adjacent to one another, and the block interleaver 124 interleaves by writing the adjacent at least one group on the same column.

Accordingly, the modulator 130 may generate a modulation symbol by mapping a bit output from a predetermined column of the block interleaver 124 onto a predetermined bit of the modulation symbol. In this case, bits included in one group may be mapped onto one bit of each modulation symbol or may be mapped onto two bits of each modulation symbol.

To explain detail, a case in which an LDPC codeword having a length of 64800 is modulated in the non-uniform 256-QAM method will be explained.

The group interleaver 122 divides the LDPC codeword into 64800/360(=180) groups, and interleaves the plurality of groups in group units.

In this case, the group interleaver 122 determines the number of groups to be written in each column of the block interleaver 124 based on the number of columns of the block interleaver 124, and interleaves the plurality of groups in group units based on the determined number of groups.

Herein, groups written in a same column of the block interleaver 124 may be mapped onto a single specific bit or two specific bits from among bits constituting each modulation symbol according to the number of columns of the block interleaver 124. Thus, the group interleaver 122 interleaves the plurality of groups in group units such that groups including bits required to be mapped onto a predetermined bit of each modulation symbol are adjacent to one another and serially arranged, considering bit characteristic of the modulation symbol. In this case, the group interleaver 122 may use the above-described Table 14 to perform interleaving.

Accordingly, the groups which are adjacent to one another in the LDPC codeword interleaved in group units may be written in the same column of the block interleaver 124, and the bits written in the same column may be mapped onto a single specific bit or two specific bits of each modulation symbol by the modulator 130.

For example, it is assumed that the block interleaver 124 includes as many columns as the number of bits constituting a modulation symbol, that is, eight (8) columns. In this case, each column of the block interleaver 124 may be divided into a first part including 7920 rows and a second part including 180 rows, as shown in Table 16 or Table 20.

Accordingly, the group interleaver 122 performs group interleaving such that 7920/360(=22) groups to be written in the first part of each column of the block interleaver 124 from among the plurality of groups are serially arranged to be adjacent to one another. Accordingly, the block interleaver 124 writes 22 groups on the first part of each column and divides the bits included in the other 4 groups and writes these bits on the second part of each column.

Thereafter, the block interleaver 124 reads the bits written in each row of the first part of the plurality of columns in the row direction, and reads the bits written in each row of the second part of the plurality of columns in the row direction.

That is, the block interleaver 124 may output the bits written in each row of the plurality of columns, from the bit written in the first row of the first column to the bit written in the first row of the sixth column, serially like (q₀,q₁,q₂,q₃,q₄,q₅,q₆,q₇,q₈,q₉,q₁₀,q₁₁, . . . ).

In this case, when the demultiplexer (not shown) is not used or the demultiplexer (not shown) outputs serially bits input to the demultiplexer (not shown) without changing the order of the bits, the LDPC codeword bits output from the block interleaver 124, (q₀,q₁,q₂,q₃,q₄,q₅,q₆,q₇), (q₈,q₉,q₁₀,q₁₁,q₁₂,q₁₃,q₁₄,q₁₅), . . . , etc. are modulated by the modulator 130. That is, the LDPC codeword bits output from the block interleaver 124, (q₀,q₁,q₂,q₃,q₄,q₅,q₆,q₇), (q₈,q₉,q₁₀,q₁₁,q₁₂,q₁₃,q₁₄,q₁₅), . . . , etc. configure cells (y_(0,0),y_(1,0), . . . ,y_(7,0)), (y_(0,1),y_(1,1) . . . , y_(7,1)), . . . , etc. and the modulator 130 generates a modulation symbol by mapping the cells onto constellation points.

Accordingly, the modulator 130 may map bits output from a same column of the block interleaver 124 onto a single specific bit of bits constituting each modulation symbol. For example, the modulator 130 may map bits included in a group written in the first column of the block interleaver 124, that is, (q₀, q₈, . . . ), onto the first bit of each modulation symbol, and also, bits written in the first column may be bits which are determined to be mapped onto the first bit of each modulation symbol according to a codeword characteristic of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.

As described above, the group interleaver 122 may interleave a plurality of groups of an LDPC codeword in group units such that the groups including bits to be mapped onto a single bit of a specific location of each modulation symbol are written in a specific column of the block interleaver 124.

Hereinafter, exemplary embodiments will be explained in detail.

First, according to an exemplary embodiment, it is assumed that the encoder 110 performs LDPC encoding at a code rate of 6/15, 7/15, 8/15 and 9/15 and generates an LDPC codeword formed of 64800 bits (N_(ldpc)=64800), and the modulator 130 uses the non-uniform 256-QAM modulation method corresponding to the code rate based on Table 34.

In this case, the group interleaver 122 may perform group interleaving by using Equation 11 and Table 14. The block interleaver 124 in which the number of columns is eight (8), the number of rows of the first part is 7920(=360×22), and the number of rows of the second part is 180 according to Table 16 or 20 may be used.

Accordingly, 2 groups (X₉, X₆, X₁₆₀, X₇₈, X₁, X₃₅, X₁₀₂, X₁₀₄, X₈₆, X₁₄₅, X₁₁₁, X₅₈, X₁₆₆, X₁₆₁, X₉₂, X₂, X₁₂₄, X₇₄, X₁₁₇, X₁₉, X₁₆₈, X₇₃) constituting an LDPC codeword are input to the first part of the first column of the block interleaver 124, 22 groups (X₁₂₂, X₃₂, X₁₃₉, X₄₂, X₄₀, X₁₀₅, X₁₀₀, X₁₄₄, X₁₁₅, X₁₅₄, X₁₃₆, X₉₇, X₁₅₅, X₂₄, X₄₁, X₁₃₈, X₁₂₈, X₈₉, X₅₀, X₈₀, X₄₉, X₂₆) are input to the first part of the second column of the block interleaver 124, 22 groups (X₆₄, X₇₅, X₁₆₉, X₁₄₆, X₀, X₃₃, X₉₈, X₇₂, X₅₉, X₁₂₀, X₁₇₃, X₉₆, X₄₃, X₁₂₉, X₄₈, X₁₀, X₁₄₇, X₅, X₂₅, X₅₆, X₈₃, X₁₆) are input to the first part of the third column of the block interleaver 124, and 22 groups (X₆₇, X₁₁₄, X₁₁₂, X₉₀, X₁₅₂, X₁₁, X₁₇₄, X₂₉, X₁₁₀, X₁₄₃, X₅, X₃₈, X₈₅, X₇₀, X₄₇, X₁₃₃, X₉₄, X₅₃, X₉₉, X₁₆₂, X₂₇, X₁₇₀) are input to the first part of the fourth column of the block interleaver 124. In addition, 22 groups X₁₆₃, X₅₇, X₁₃₁, X₃₄, X₁₀₇, X₆₆, X₁₇₁, X₁₃₀, X₆₅, X₃, X₁₇, X₃₇, X₁₂₁, X₁₈, X₁₁₃, X₅₁, X₁₅₃, X₁₀₁, X₈₁, X₁₂₃, X₄, X₂₁) are input to the first part of the fifth column of the block interleaver, 22 groups (X₄₆, X₅₅, X₂₀, X₈₈, X₁₅, X₁₀₈, X₁₆₅, X₁₅₈, X₈₇, X₁₃₇, X₁₂, X₁₂₇, X₆₈, X₆₉, X₈₂, X₁₅₉, X₇₆, X₅₄, X₁₅₇, X₁₁₉, X₁₄₀, X₉₃) are input to the first part of the sixth column of the block interleaver 124, 22 groups (X₁₀₆, X₆₂, X₉₅, X₁₆₄, X₁₄₁, X₁₅₀, X₂₃, X₁₇₂, X₉₁, X₇₁, X₆₁, X₁₂₆, X₆₀, X₁₀₃, X₁₄₉, X₈₄, X₁₁₈, X₃₉, X₇₇, X₁₁₆, X₂₂, X₂₈) are input to the first part of the seventh column of the block interleaver 124, and 22 groups (X₆₃, X₄₅, X₄₄, X₁₅₁, X₁₃₄, X₅₂, X₁₇₅, X₁₄₂, X₁₄₈, X₁₆₇, X₁₀₉, X₃₁, X₁₅₆, X₁₄, X₇₉, X₃₆, X₁₂₅, X₁₃₅, X₁₃₂, X₃₀, X₇, X₁₃) are input to the first part of the eighth column of the block interleaver 124.

In addition, groups X₁₇₉, X₁₇₈, X₁₇₇, and X₁₇₆ are input to the second part of the block interleaver 124. Specifically, bits constituting the group X₁₇₉ are input to the rows of the first column of the second part serially and input to the rows of the second column serially, bits constituting X₁₇₈ are input to the rows of the third column of the second part and input to the rows of the fourth column serially, bits constituting X₁₇₇ are input to the rows of the fifth column of the second part serially and input to the rows of the sixth column serially, and bits constituting X₁₇₆ are input to the rows of the seventh column of the second part serially and input to the rows of the eighth column serially. In this case, each of the groups X₁₇₉, X₁₇₈, X₁₇₇, and X₁₇₆ is formed of 360 bits and 90 bits are input to the second part of each column.

In addition, the block interleaver 124 may output the bits input to the first row to the last row of each column serially, and the bits output from the block interleaver 124 may be input to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the demultiplexer (not shown) may output the input bits serially without changing the order of the bits.

Accordingly, one bit included in each of groups X₉, X₁₂₂, X₆₄, X₆₇, X₁₆₃, X₄₆, X₁₀₆, and X₆₃ constitute a single modulation symbol.

According to an exemplary embodiment, one bit included in each of the groups X₉, X₁₂₂, X₆₄, X₆₇, X₁₆₃, X₄₆, X₁₀₆, and X₆₃ constitute a single modulation symbol based on group interleaving and block interleaving. In addition to the above-described method, other methods for constituting a single modulation symbol with one bit included in each of the groups X₉, X₁₂₂, X₆₄, X₆₇, X₁₆₃, X₄₆, X₁₀₆, and X₆₃ may be included in the inventive concept.

The transmitting apparatus 100 may modulate a signal mapped onto a constellation and may transmit the signal to a receiving apparatus (for example, a receiving apparatus 2700 of FIG. 20). For example, the transmitting apparatus 100 may map a signal mapped onto a constellation onto an Orthogonal Frequency Division Multiplexing (OFDM) frame by using the OFDM method, and may transmit the signal to the receiving apparatus 2700 via an allocated channel.

To achieve this, the transmitting apparatus 100 may further include a frame mapper (not shown) to map the signal mapped onto the constellation onto the OFDM frame, and a transmitter (not shown) to transmit the signal of the OFDM frame format to the receiving apparatus 2700.

The bit interleaving method suggested in the exemplary embodiments is performed by the parity interleaver 121, the group interleaver 122, the group twist interleaver 123, and the block interleaver 124 as shown in FIG. 4 (the parity interleaver 121 or group twist interleaver 123 may be omitted according to circumstances). However, this is merely an example and the bit interleaving method is not limited to three modules or four modules described above.

For example, when the block interleaver is used and the group interleaving method expressed as in Equation 11 is used, regarding the bit groups X_(j)(0≦j<N_(group)) defined as in Equation 9 and Equation 10, bits belonging to m number of bit groups, for example, {X_(π(i)), X_(π(α+i)), . . . , X_(π((m−1)×α+i))}(0≦i<α), may constitute a single modulation symbol.

Herein, a is the number of bit groups constituting the first part of the block interleaver, and α=└N_(group)/m┘. In addition, m is the number of columns of the block interleaver and may be equal to the number of bits constituting the modulation symbol or half of the number of bits constituting the modulation symbol.

Therefore, for example, regarding parity-interleaved bits u_(i), {u_(π(i)+j), u_(π(α+i)+j), . . . , u_(π((m−1)×α+i)+j)}(0<i≦m, 0<j≦M) may constitute a single modulation symbol. As described above, there are various methods for constituting a single modulation symbol.

FIG. 20 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment. Referring to FIG. 20, the receiving apparatus 2700 includes a demodulator 2710, a multiplexer 2720, a deinterleaver 2730 and a decoder 2740.

The demodulator 2710 receives and demodulates a signal transmitted from the transmitting apparatus 100. Specifically, the demodulator 2710 generates a value corresponding to an LDPC codeword by demodulating the received signal, and outputs the value to the multiplexer 2720. In this case, the demodulator 2710 may use a demodulation method corresponding to a modulation method used in the transmitting apparatus 100.

To do so, the transmitting apparatus 100 may transmit information regarding the modulation method to the receiving apparatus 2700, or the transmitting apparatus 100 may perform demodulation using a pre-defined modulation method between the transmitting apparatus 100 and the receiving apparatus 2700.

The value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There are various methods for determining the channel value, and for example, a method for determining a Log Likelihood Ratio (LLR) value may be the method for determining the channel value.

The LLR value is a log value for a ratio of the probability that a bit transmitted from the transmitting apparatus 100 is 0 and the probability that the bit is 1. In addition, the LLR value may be a bit value which is determined by a hard decision, or may be a representative value which is determined according to a section to which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 belongs.

The multiplexer 2720 multiplexes the output value of the demodulator 2710 and outputs the value to the deinterleaver 2730.

Specifically, the multiplexer 2720 is an element corresponding to a demultiplexer (not shown) provided in the transmitting apparatus 100, and performs an operation corresponding to the demultiplexer (not shown). Accordingly, when the demultiplexer (not shown) is omitted from the transmitting apparatus 100, the multiplexer 2720 may be omitted from the receiving apparatus 2700.

That is, the multiplexer 2720 converts the output value of the demodulator 2710 into cell-to-bit and outputs an LLR value on a bit basis.

In this case, when the demultiplexer (not shown) does not change the order of the LDPC codeword bits as shown in FIG. 13, the multiplexer 2720 may output the LLR values serially on the bit basis without changing the order of the LLR values corresponding to the bits of the cell. Alternatively, the multiplexer 2720 may rearrange the order of the LLR values corresponding to the bits of the cell to perform an inverse operation to the demultiplexing operation of the demultiplexer (not shown) based on Table 22. Meanwhile, the information regarding whether the demultiplexing operation is performed may be provided by the transmitting apparatus 100, or may be pre-defined between the transmitting apparatus 100 and the receiving apparatus 2700.

The deinterleaver 2730 deinterleaves the output value of the multiplexer 2720 and outputs the values to the decoder 2740.

Specifically, the deinterleaver 2730 is an element corresponding to the interleaver 120 of the transmitting apparatus 100 and performs an operation corresponding to the interleaver 120. That is, the deinterleaver 2730 deinterleaves the LLR value by performing the interleaving operation of the interleaver 120 inversely.

To do so, the deinterleaver 2730 may include a block deinterleaver 2731, a group twist deinterleaver 2732, a group deinterleaver 2733, and a parity deinterleaver 2734 as shown in FIG. 21.

The block deinterleaver 2731 deinterleaves the output of the multiplexer 2720 and outputs a value to the group twist deinterleaver 2732.

Specifically, the block deinterleaver 2731 is an element corresponding to the block interleaver 124 provided in the transmitting apparatus 100 and performs the interleaving operation of the block interleaver 124 inversely.

That is, the block deinterleaver 2731 deinterleaves by using at least one row formed of a plurality of columns, that is, by writing the LLR value output from the multiplexer 2720 in each row in the row direction and reading each column of the plurality of rows in which the LLR value is written in the column direction.

In this case, when the block interleaver 124 interleaves by dividing a column into two parts, the block deinterleaver 2731 may deinterleave by dividing a row into two parts.

Hereinafter, the block deinterleaver 2731 will be explained with reference to FIG. 22. However, this is merely an example and the block deinterleaver 2731 may be implemented in other methods.

An input LLR v_(i) (0≦i<N_(ldpc)) is written in a r_(i) row and a c_(i) column of the block deinterleaver 2431. Herein, c_(i)=(i mod N_(c)) and

${r_{i} = \left\lfloor \frac{i}{N_{c}} \right\rfloor},$

On the other hand, an output LLR q_(i)(0≦i<N_(c)×N_(r1)) is read from a c_(i) column and a r_(i) row of the first part of the block deinterleaver 2431. Herein,

${c_{i} = \left\lfloor \frac{i}{N_{r\; 1}} \right\rfloor},$

r_(i)=(i mod N_(r1))

In addition, an output LLR q_(i)(N_(c)×N_(r1)≦i<N_(ldpc)) is read from a c_(i) column and a r_(i) row of the second part. Herein,

${c_{i} = \left\lfloor \frac{\left( {i - {N_{c} \times N_{r\; 1}}} \right)}{N_{r\; 2}} \right\rfloor},$

r_(i)=N_(r1)+{(i−N_(c)×N_(r1)) mode N_(r2)}.

The group twist deinterleaver 2732 deinterleaves the output value of the block deinterleaver 2731 and outputs the value to the group deinterleaver 2733.

Specifically, the group twist deinterleaver 2732 is an element corresponding to the group twist interleaver 123 provided in the transmitting apparatus 100, and may perform the interleaving operation of the group twist interleaver 123 inversely.

That is, the group twist deinterleaver 2732 may rearrange the LLR values of the same group by changing the order of the LLR values existing in the same group. When the group twist operation is not performed in the transmitting apparatus 100, the group twist deinterleaver 2732 may be omitted.

The group deinterleaver 2733 (or the group-wise deinterleaver) deinterleaves an output value of the group twist deinterleaver 2732 and outputs a value to the parity deinterleaver 2734.

Specifically, the group deinterleaver 2733 is an element corresponding to the group interleaver 122 provided in the transmitting apparatus 100 and may perform the interleaving operation of the group interleaver 122 inversely.

That is, the group deinterleaver 2733 may rearrange the order of the plurality of groups in group units. In this case, the group deinterleaver 2733 may rearrange the order of the plurality of groups in group units by applying the interleaving method of Tables 12 to 15 inversely according to a length of the LDPC codeword, a modulation method and a code rate.

As described above, in the parity check matrix having the format shown in FIGS. 2 and 3, the order of column groups is changeable and the column group corresponds to a bit group. Accordingly, when the order of column groups of the parity check matrix is changed, the order of bit groups is changed accordingly and the group deinterleaver 2733 may rearrange the order of the plurality of groups in group units with reference to this.

The parity deinterleaver 2734 performs parity deinterleaving with respect to an output value of the group deinterleaver 2733 and outputs a value to the decoder 2740.

Specifically, the parity deinterleaver 2734 is an element corresponding to the parity interleaver 121 provided in the transmitting apparatus 100 and may perform the interleaving operation of the parity interleaver 121 inversely. That is, the parity deinterleaver 2734 may deinterleave the LLR values corresponding to the parity bits from among the LLR values output from the group deinterleaver 2733. In this case, the parity deinterleaver 2734 may be omitted depending on the decoding method and embodiment of the decoder 2740.

To do so, the transmitting apparatus 100 may transmit various pieces of information which are used for interleaving in the interleaver 120 to the receiving apparatus 2700, or may perform interleaving using a pre-defined method between the transmitting apparatus 100 and the receiving apparatus 2700.

Although the deinterleaver 2730 of FIG. 24 includes three (3) or four (4) elements as shown in FIG. 25, operations of the elements may be performed by a single element. For example, when bits each of which belongs to each of bit groups X_(a), X_(b), X_(c), and X_(d) constitute a single modulation symbol, the deinterleaver 2730 may deinterleave these bits to locations corresponding to their bit groups based on the received single modulation symbol.

For example, when a code rate is 7/15 and a modulation method is 256-QAM, the group deinterleaver 2733 may perform deinterleaving based on table 14.

In this case, bits each of which belongs to each of bit groups X₉, X₁₂₂, X₆₄, X₆₇, X₁₆₃, X₄₆, X₁₀₆, and X₆₃ constitute a single modulation symbol. Since one bit in each of the bit groups X₉, X₁₂₂, X₆₄, X₆₇, X₁₆₃, X₄₆, X₁₀₆, and X₆₃ constitutes a single modulation symbol, the deinterleaver 2730 may map bits onto decoding initial values corresponding to the bit groups X₉, X₁₂₂, X₆₄, X₆₇, X₁₆₃, X₄₆, X₁₀₆, and X₆₃ based on the received single modulation symbol.

The decoder 2740 may perform LDPC decoding by using the output value of the deinterleaver 2730. To achieve this, the decoder 2740 may include a separate LDPC decoder (not shown) to perform the LDPC decoding.

Specifically, the decoder 2740 is an element corresponding to the encoder 110 of the transmitting apparatus 200 and may correct an error by performing the LDPC decoding by using the LLR value output from the deinterleaver 2730.

For example, the decoder 2740 may perform the LDPC decoding in an iterative decoding method based on a sum-product algorithm. The sum-product algorithm is one example of a message passing algorithm, and the message passing algorithm refers to an algorithm which exchanges messages (e.g., LLR value) through an edge on a bipartite graph, calculates an output message from messages input to variable nodes or check nodes, and updates.

The decoder 2740 may use a parity check matrix when performing the LDPC decoding. In this case, an information word submatrix in the parity check matrix is defined as in Tables 4 to 11 according to a code rate and a length of the LDPC codeword, and a parity submatrix may have a dual diagonal configuration.

In addition, information on the parity check matrix and information on the code rate, etc. which are used in the LDPC decoding may be pre-stored in the receiving apparatus 2700 or may be provided by the transmitting apparatus 100.

FIG. 23 is a flowchart to illustrate a signal processing method according to an exemplary embodiment.

First of all, an LDPC codeword is generated by performing LDPC encoding (S3010).

Subsequently, the LDPC codeword is interleaved (S3020), and a modulation symbol is generated by modulating the interleaved LDPC codeword according to a modulation method (S3030).

Herein, in S3020, the interleaving interleaves a plurality of bit groups constituting the LDPC codeword by dividing each of a plurality of columns including each of a plurality of rows into a first part and a second part, all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part, and at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns constituting the second part.

In this case, the number of the plurality of columns may be a same as a modulation degree according to the modulation method, and each of the plurality of columns may be formed of rows of which number is the number of bits constituting an LDPC codeword divided by the number of the plurality of columns.

In addition, the first part may be formed of rows of which number is the number of bits included in at least a part of bit groups which are writable in each of the plurality of columns by a bit group unit from among a plurality of bit groups constituting the LDPC codeword according to the number of columns constituting the block interleaver, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group, from each of the plurality of columns, and the second part may be formed of rows excluding the number of rows as many as the number of bits included in at least a part of bit groups which are writable in each of the plurality of columns in bit group units from rows constituting each of the plurality of columns, from each of the plurality of columns.

In addition, the number of rows of the second part may be a same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver.

In addition, the interleaving may include writing the bits included in at least a part of bit groups which are writable in bit group units in each of a plurality of columns constituting the first part sequentially, dividing bits included in remaining bit groups excluding at least a part of bit groups from a plurality of bit groups based on the number of the plurality of columns, and writing the bits in each of a plurality of columns constituting the second part sequentially.

In addition, the interleaving may include dividing bits included in the remaining bit groups by the number of the plurality of columns, writing each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and performing interleaving by reading a plurality of columns constituting the second part in a row direction.

In addition, the modulation degree may be 2, 4, 6, 8, 10, or 12 when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM, respectively.

A non-transitory computer readable medium, which stores a program for performing the above signal processing methods according to various exemplary embodiments in sequence, may be provided.

The non-transitory computer readable medium refers to a medium that stores data semi-permanently rather than storing data for a very short time, such as a register, a cache, and a memory, and is readable by an apparatus. Specifically, the above-described various applications or programs may be stored in a non-transitory computer readable medium such as a compact disc (CD), a digital versatile disk (DVD), a hard disk, a Blu-ray disk, a universal serial bus (USB), a memory card, and a read only memory (ROM), and may be provided.

Components, elements or units represented by a block as illustrated in FIGS. 1, 4, 12, 13, 23 and 27-29 may be embodied as the various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to exemplary embodiments. For example, these components, elements or units may use a direct circuit structure, such as a memory, processing, logic, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. These components, elements or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions. Also, at least one of the above components, elements or units may further include a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like.

Although a bus is not illustrated in the block diagrams of the transmitting apparatus and the receiving apparatus, communication may be performed between each element of each apparatus via the bus. In addition, each apparatus may further include a processor such as a Central Processing Unit (CPU) or a microprocessor to perform the above-described various operations.

The foregoing exemplary embodiments and advantages are merely exemplary and are not to be construed as limiting the present inventive concept. The exemplary embodiments can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments is intended to be illustrative, and not to limit the scope of the inventive concept, and many alternatives, modifications, and variations will be apparent to those skilled in the art. 

What is claimed is:
 1. A transmitting apparatus comprising: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol, wherein the interleaver is formed of a plurality of columns including a plurality of rows, respectively, and comprises: a block interleaver configured to divide each of the plurality of columns into a first part and a second part, and interleave a plurality of bit groups constituting the LDPC codeword, wherein all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part, wherein at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns constituting the second part.
 2. The transmitting apparatus of claim 1, wherein the number of the plurality of columns is a same as a modulation degree according to the modulation method, wherein each of the plurality of columns is formed of rows of which number is the number of bits constituting an LDPC codeword divided by the number of the plurality of columns.
 3. The transmitting apparatus of claim 1, wherein the first part is formed of rows of which number is the number of bits included in at least a part of bit groups which are writable in each of the plurality of columns by a bit group unit from among a plurality of bit groups constituting the LDPC codeword according to the number of columns constituting the block interleaver, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group, from each of the plurality of columns, wherein the second part is formed of rows excluding the number of rows as many as the number of bits included in at least a part of bit groups which are writable in each of the plurality of columns in bit group units from rows constituting each of the plurality of columns, from each of the plurality of columns.
 4. The transmitting apparatus of claim 3, wherein the number of rows of the second part is a same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver.
 5. The transmitting apparatus of claim 3, wherein the block interleaver writes the bits included in at least a part of bit groups which are writable in bit group units in each of a plurality of columns constituting the first part sequentially, divides bits included in remaining bit groups excluding at least a part of bit groups from a plurality of bit groups based on the number of the plurality of columns, and writes the bits in each of a plurality of columns constituting the second part sequentially.
 6. The transmitting apparatus of claim 4, wherein the block interleaver divides bits included in the remaining bit groups by the number of the plurality of columns, writes each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and performs interleaving by reading a plurality of columns constituting the second part in a row direction.
 7. The transmitting apparatus of claim 2, wherein the modulation degree are 2, 4, 6, 8, 10, or 12 when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM, respectively.
 8. A method for processing a signal of a transmitting apparatus, the method comprising: generating an LDPC codeword by performing LDPC encoding; interleaving the LDPC codeword; and generating a modulation symbol by modulating the interleaved LDPC codeword according to a modulation method, wherein the interleaving interleaves a plurality of bit groups constituting the LDPC codeword by dividing each of a plurality of columns including each of a plurality of rows into a first part and a second part, wherein all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part, wherein at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns constituting the second part.
 9. The method of claim 8, wherein the number of the plurality of columns is a same as a modulation degree according to the modulation method, wherein each of the plurality of columns is formed of rows of which number is the number of bits constituting an LDPC codeword divided by the number of the plurality of columns.
 10. The method of claim 8, wherein the first part is formed of rows of which number is the number of bits included in at least a part of bit groups which are writable in each of the plurality of columns by a bit group unit from among a plurality of bit groups constituting the LDPC codeword according to the number of columns constituting the block interleaver, the number of bit groups constituting the LDPC codeword, and the number of bits constituting each bit group, from each of the plurality of columns, wherein the second part is formed of rows excluding the number of rows as many as the number of bits included in at least a part of bit groups which are writable in each of the plurality of columns in bit group units from rows constituting each of the plurality of columns, from each of the plurality of columns.
 11. The method of claim 10, wherein the number of rows of the second part is a same value as a quotient when the number of bits included in all bit groups excluding bit groups corresponding to the first part is divided by the number of columns constituting the block interleaver.
 12. The method of claim 10, wherein the interleaving comprises writing the bits included in at least a part of bit groups which are writable in bit group units in each of a plurality of columns constituting the first part serially, dividing bits included in remaining bit groups excluding at least a part of bit groups from a plurality of bit groups based on the number of the plurality of columns, and writing the bits in each of a plurality of columns constituting the second part serially.
 13. The method of claim 9, wherein the interleaving comprises dividing bits included in the remaining bit groups by the number of the plurality of columns, writing each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and performing interleaving by reading a plurality of columns constituting the second part in a row direction.
 14. The method of claim 9, wherein the modulation degree are 2, 4, 6, 8, 10, or 12 when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, or 4096-QAM, respectively. 